公开(公告)号：US20250046384A1

公开(公告)日：2025-02-06

申请号：US18923698

申请日：2024-10-23

Applicant: Kioxia Corporation

Inventor： Akio SUGAHARA ,  Takaya HANDA ,  Ryosuke ISOMURA ,  Kazuto UEHARA ,  Junichi SATO ,  Norichika ASAOKA ,  Masashi YAMAOKA ,  Bushnaq SANAD ,  Yuzuru SHIBAZAKI ,  Noriyasu KUMAZAKI ,  Yuri TERADA

IPC: G11C16/30 ,  G11C16/04 ,  G11C16/08 ,  G11C16/12 ,  G11C16/26 ,  G11C16/32 ,  H10B69/00

Abstract: A memory device includes a memory cell array, a voltage generation circuit generating one or more voltages supplied to the memory cell array, an input/output circuit receiving a first command and an address indicating a region in the memory cell array, and a control circuit controlling a read operation to the memory cell array based on the first command. The control circuit supplies a non-selection voltage of the voltages before a ready/busy signal changes from a ready state to a busy state.

公开(公告)号：US12205900B2

公开(公告)日：2025-01-21

申请号：US17664385

申请日：2022-05-20

Applicant: Micron Technology, Inc.

Inventor： Jivaan Kishore Jhothiraman ,  Rutuparna Narulkar ,  Chandra S. Tiwari

IPC: H01L23/532 ,  H01L21/768 ,  H01L21/02 ,  H10B69/00

Abstract: An electronic device includes a stack structure, the stack structure including at least one deck including tiers of vertically alternating dielectric materials and conductive materials, an opening extending through the at least one deck, a compressive dielectric material disposed on a bottom surface defining the opening and on sidewalls of the tiers defining the opening, and a dielectric material in direct contact with the compressive dielectric material. The dielectric material substantially fills a remainder of the opening. The compressive dielectric material exhibits a horizontal compressive force against the tiers. Related methods and systems are also disclosed.

公开(公告)号：US12171093B2

公开(公告)日：2024-12-17

申请号：US18377794

申请日：2023-10-07

Applicant: Zeno Semiconductor, Inc.

Inventor： Benjamin S. Louie ,  Jin-Woo Han ,  Yuniarto Widjaja

IPC: H10B12/00 ,  G11C5/06 ,  G11C11/4096 ,  G11C11/4099 ,  G11C16/04 ,  H01L21/265 ,  H01L23/528 ,  H01L27/088 ,  H01L29/10 ,  H01L29/66 ,  H01L29/78 ,  H10B41/35 ,  H10B43/35 ,  H10B69/00

Abstract: NAND string configurations and semiconductor memory arrays that include such NAND string configurations are provided. Methods of making semiconductor memory cells used in NAND string configurations are also described.

公开(公告)号：US12159677B2

公开(公告)日：2024-12-03

申请号：US18205915

申请日：2023-06-05

Applicant: Kioxia Corporation

Inventor： Akio Sugahara ,  Takaya Handa ,  Ryosuke Isomura ,  Kazuto Uehara ,  Junichi Sato ,  Norichika Asaoka ,  Masashi Yamaoka ,  Bushnaq Sanad ,  Yuzuru Shibazaki ,  Noriyasu Kumazaki ,  Yuri Terada

IPC: G11C16/30 ,  G11C16/04 ,  G11C16/08 ,  G11C16/32 ,  G11C16/12 ,  G11C16/26 ,  H10B69/00

Abstract: A memory device includes a memory cell array, a voltage generation circuit generating one or more voltages supplied to the memory cell array, an input/output circuit receiving an address indicating a region in the memory cell array, and a control circuit controlling operations of the memory cell array. The control circuit supplies a non-selection voltage of the voltages before a ready/busy signal changes from a ready state to a busy state.

公开(公告)号：US12101945B2

公开(公告)日：2024-09-24

申请号：US18225186

申请日：2023-07-24

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Tomoaki Atsumi ,  Shuhei Nagatsuka ,  Tamae Moriwaka ,  Yuta Endo

IPC: H10B69/00 ,  G11C7/16 ,  G11C8/14 ,  G11C11/24 ,  G11C11/403 ,  G11C11/408 ,  H01L27/06 ,  H01L29/24 ,  H01L29/786 ,  H10B41/20 ,  H10B41/70

CPC classification number: H10B69/00 ,  G11C7/16 ,  G11C8/14 ,  G11C11/24 ,  G11C11/403 ,  G11C11/4085 ,  H01L27/0688 ,  H01L29/24 ,  H01L29/7869 ,  H10B41/20 ,  H10B41/70

Abstract: [Problem] To provide a semiconductor device suitable for miniaturization. To provide a highly reliable semiconductor device. To provide a semiconductor device with improved operating speed.
[Solving Means] A semiconductor device including a memory cell including first to cth (c is a natural number of 2 or more) sub memory cells, wherein: the jth sub memory cell includes a first transistor, a second transistor, and a capacitor; a first semiconductor layer included in the first transistor and a second semiconductor layer included in the second transistor include an oxide semiconductor; one of terminals of the capacitor is electrically connected to a gate electrode included in the second transistor; the gate electrode included in the second transistor is electrically connected to one of a source electrode and a drain electrode which are included in the first transistor; and when j≥2, the jth sub memory cell is arranged over the j−1th sub memory cell.

公开(公告)号：US20240266445A1

公开(公告)日：2024-08-08

申请号：US18638923

申请日：2024-04-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinseong HEO ,  Taehwan MOON ,  Hagyoul BAE ,  Seunggeol NAM ,  Sangwook KIM ,  Kwanghee LEE

IPC: H01L29/86 ,  H10B69/00 ,  H10K10/50 ,  H10K19/00

CPC classification number: H01L29/86 ,  H10B69/00 ,  H10K10/50 ,  H10K19/00 ,  H10K19/201

Abstract: A semiconductor apparatus includes a plurality of semiconductor devices. The semiconductor devices each include a ferroelectric layer, a conductive metal oxide layer, and a semiconductor layer, between two electrodes. The conductive metal oxide layer may be between the ferroelectric layer and the semiconductor layer. The ferroelectric layer, the conductive metal oxide layer, and the semiconductor layer may all include a metal oxide. The conductive metal oxide layer may include one or more materials selected from the group consisting of an indium oxide, a zinc oxide, a tin oxide, and any combination thereof.

公开(公告)号：US12027643B2

公开(公告)日：2024-07-02

申请号：US17232287

申请日：2021-04-16

Applicant: ALEDIA ,  COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

Inventor： Eric Pourquier ,  Hubert Bono

IPC: H01L33/08 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/02 ,  H01L27/15 ,  H01L29/06 ,  H01L29/12 ,  H01L29/66 ,  H01L33/00 ,  H01L33/06 ,  H01L33/16 ,  H01L33/18 ,  H01L33/24 ,  H01L33/42 ,  H01L33/48 ,  H10B69/00 ,  H01L33/02

CPC classification number: H01L33/06 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/02603 ,  H01L27/15 ,  H01L29/0676 ,  H01L29/068 ,  H01L29/125 ,  H01L29/127 ,  H01L29/6609 ,  H01L29/66469 ,  H01L33/0008 ,  H01L33/0062 ,  H01L33/007 ,  H01L33/0095 ,  H01L33/08 ,  H01L33/16 ,  H01L33/18 ,  H01L33/24 ,  H01L33/42 ,  H01L33/48 ,  H10B69/00 ,  H01L33/02 ,  H01L2924/0002 ,  H01L2933/0016 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A process for producing at least two adjacent regions, each comprising an array of light-emitting wires connected together in a given region by a transparent conductive layer, comprises: producing, on a substrate, a plurality of individual zones for growing wires extending over an area greater than the cumulative area of the two chips; growing wires in the individual growth zones; removing wires from at least one zone forming an initial free area to define the arrays of wires, the initial free area comprising individual growth zones level with the removed wires; and depositing a transparent conductive layer on each array of wires to electrically connect the wires of a given array of wires, each conductive layer being separated from the conductive layer of the neighbouring region by a free area. A device obtained using the process of the invention is also provided.

公开(公告)号：US20240188307A1

公开(公告)日：2024-06-06

申请号：US18441204

申请日：2024-02-14

Applicant: Kioxia Corporation

Inventor： Masahiro KIYOTOSHI ,  Akihito YAMAMOTO ,  Yoshio OZAWA ,  Fumitaka ARAI ,  Riichiro SHIROTA

IPC: H10B63/00 ,  H01L21/02 ,  H01L21/28 ,  H01L21/306 ,  H01L21/3105 ,  H01L21/321 ,  H01L21/3213 ,  H01L21/762 ,  H01L27/105 ,  H01L29/51 ,  H10B43/27 ,  H10B43/30 ,  H10B43/35 ,  H10B43/40 ,  H10B69/00 ,  H10B99/00 ,  H10N70/00 ,  H10N70/20

CPC classification number: H10B63/845 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/30604 ,  H01L21/31055 ,  H01L21/3212 ,  H01L21/32136 ,  H01L21/762 ,  H01L27/105 ,  H01L29/40117 ,  H01L29/513 ,  H01L29/518 ,  H10B43/27 ,  H10B43/30 ,  H10B43/35 ,  H10B43/40 ,  H10B63/00 ,  H10B63/20 ,  H10B63/30 ,  H10B69/00 ,  H10B99/00 ,  H10N70/021 ,  H10N70/231 ,  H10N70/801 ,  H10N70/882 ,  H10N70/028 ,  H10N70/20 ,  H10N70/823 ,  H10N70/8413 ,  H10N70/8828 ,  H10N70/8833

Abstract: A semiconductor memory includes a plurality of stripe-like active areas formed by stacking, in a direction perpendicular to a substrate, a plurality of layers extending parallel to the substrate, a first gate electrode formed on first side surfaces of the active areas, the first side surfaces being perpendicular to the substrate, a second gate electrode formed on second side surfaces of the active areas, the second side surfaces being perpendicular to the substrate. The layers are patterned in self-alignment with each other, intersections of the active areas and the first gate electrode form a plurality of memory cells, and the plurality of memory cells in an intersecting plane share the first gate electrode.

公开(公告)号：US11903205B2

公开(公告)日：2024-02-13

申请号：US17744571

申请日：2022-05-13

Applicant: Kioxia Corporation

Inventor： Masaru Kito ,  Hideaki Aochi ,  Ryota Katsumata ,  Akihiro Nitayama ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Yoshiaki Fukuzumi ,  Yasuyuki Matsuoka ,  Mitsuru Sato

IPC: H10B43/27 ,  H01L21/822 ,  H01L27/06 ,  H01L27/105 ,  H10B41/27 ,  H10B43/20 ,  H10B43/40 ,  H10B69/00 ,  G11C16/04

CPC classification number: H10B43/27 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/105 ,  H10B41/27 ,  H10B43/20 ,  H10B43/40 ,  H10B69/00 ,  G11C16/0483

Abstract: A nonvolatile semiconductor memory device that have a new structure are provided, in which memory cells are laminated in a three dimensional state so that the chip area may be reduced. The nonvolatile semiconductor memory device of the present invention is a nonvolatile semiconductor memory device that has a plurality of the memory strings, in which a plurality of electrically programmable memory cells is connected in series. The memory strings comprise a pillar shaped semiconductor; a first insulation film formed around the pillar shaped semiconductor; a charge storage layer formed around the first insulation film; the second insulation film formed around the charge storage layer; and first or nth electrodes formed around the second insulation film (n is natural number more than 1). The first or nth electrodes of the memory strings and the other first or nth electrodes of the memory strings are respectively the first or nth conductor layers that are spread in a two dimensional state.

公开(公告)号：US11869965B2

公开(公告)日：2024-01-09

申请号：US18227183

申请日：2023-07-27

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach

IPC: H01L29/78 ,  G11C16/02 ,  G11C11/404 ,  G11C11/4097 ,  H10B10/00 ,  H10B12/00 ,  H10B43/20 ,  H10B69/00 ,  H10B63/00 ,  G11C11/412 ,  G11C16/04

CPC classification number: H01L29/78 ,  G11C11/404 ,  G11C11/4097 ,  G11C16/02 ,  H01L29/7841 ,  H10B10/12 ,  H10B12/20 ,  H10B43/20 ,  H10B63/30 ,  H10B69/00 ,  G11C11/412 ,  G11C16/0483 ,  G11C2213/71

Abstract: A 3D semiconductor device including: a first level including a first single crystal layer and first transistors, and at least one first metal layer-which includes interconnects between the first transistors forming control circuits-which overlays the first single crystal layer; a second metal layer overlaying first metal layer; a second level including second transistors, first memory cells (each including at least one second transistor) and overlaying second metal layer; a third level including third transistors (at least one includes a polysilicon channel), second memory cells (each including at least one third transistor and cell is partially disposed atop control circuits) and overlaying the second level; control circuits control data written to second memory cells; third metal layer disposed above third level; fourth metal layer includes a global power distribution grid, has a thickness at least twice the second metal layer, and is disposed above third metal layer.