公开(公告)号：US12159677B2

公开(公告)日：2024-12-03

申请号：US18205915

申请日：2023-06-05

Applicant: Kioxia Corporation

Inventor： Akio Sugahara ,  Takaya Handa ,  Ryosuke Isomura ,  Kazuto Uehara ,  Junichi Sato ,  Norichika Asaoka ,  Masashi Yamaoka ,  Bushnaq Sanad ,  Yuzuru Shibazaki ,  Noriyasu Kumazaki ,  Yuri Terada

IPC: G11C16/30 ,  G11C16/04 ,  G11C16/08 ,  G11C16/32 ,  G11C16/12 ,  G11C16/26 ,  H10B69/00

Abstract: A memory device includes a memory cell array, a voltage generation circuit generating one or more voltages supplied to the memory cell array, an input/output circuit receiving an address indicating a region in the memory cell array, and a control circuit controlling operations of the memory cell array. The control circuit supplies a non-selection voltage of the voltages before a ready/busy signal changes from a ready state to a busy state.

公开(公告)号：US11694754B2

公开(公告)日：2023-07-04

申请号：US17469095

申请日：2021-09-08

Applicant: Kioxia Corporation

Inventor： Yuzuru Shibazaki

IPC: G11C7/00 ,  G11C16/32 ,  G11C16/34 ,  G11C16/10 ,  G11C16/04

CPC classification number: G11C16/32 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3459

Abstract: ABSTRACT A semiconductor memory device provides a first memory cell array including a plurality of first memory blocks, a second memory cell array comprising a plurality of second memory blocks, and a voltage supply line electrically connected to the plurality of first memory blocks and the plurality of second memory blocks. Moreover, this semiconductor memory device is configured to execute a write operation. At a first timing of this write operation, the voltage supply line is not electrically continuous with the first and second memory blocks. Moreover, a voltage of the voltage supply line at the first timing in the case of the write operation being executed on the first and second memory blocks is larger than a voltage of the voltage supply line at the first timing in the case of the write operation being executed on the first memory block.

公开(公告)号：US11869597B2

公开(公告)日：2024-01-09

申请号：US17464297

申请日：2021-09-01

Applicant: Kioxia Corporation

Inventor： Takeshi Nakano ,  Yuzuru Shibazaki ,  Hideyuki Kataoka ,  Junichi Sato ,  Hiroki Date

IPC: G11C16/10 ,  G11C16/26 ,  G11C16/30 ,  G11C29/42 ,  G11C16/08 ,  G11C16/04 ,  G11C16/24

CPC classification number: G11C16/102 ,  G11C16/0433 ,  G11C16/08 ,  G11C16/24 ,  G11C16/26 ,  G11C16/30 ,  G11C29/42

Abstract: A semiconductor storage device in an embodiment includes a plurality of planes each including a memory cell array, a voltage generation circuit configured to apply a first intermediate voltage to an adjacent word line adjacent to a selected word line in a former half of a program period and apply a second intermediate voltage higher than the first intermediate voltage to the adjacent word line in a latter half of the program period, a discharge circuit configured to feed a discharge current from the selected word line in a period corresponding to a period in which the second intermediate voltage is applied to the adjacent word line, and a control circuit configured to set a discharge characteristic of the discharge circuit according to a number of the planes.

公开(公告)号：US11705210B2

公开(公告)日：2023-07-18

申请号：US17570676

申请日：2022-01-07

Applicant: Kioxia Corporation

Inventor： Akio Sugahara ,  Takaya Handa ,  Ryosuke Isomura ,  Kazuto Uehara ,  Junichi Sato ,  Norichika Asaoka ,  Masashi Yamaoka ,  Bushnaq Sanad ,  Yuzuru Shibazaki ,  Noriyasu Kumazaki ,  Yuri Terada

IPC: G11C16/30 ,  G11C16/04 ,  G11C16/08 ,  G11C16/26 ,  G11C16/32 ,  G11C16/12 ,  H10B69/00

CPC classification number: G11C16/30 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/32 ,  G11C16/12 ,  G11C16/26 ,  H10B69/00

Abstract: A memory device includes a memory cell array, a voltage generation circuit generating one or more voltages supplied to the memory cell array, an input/output circuit receiving an address indicating a region in the memory cell array and a control circuit controlling operations of the memory cell array. The voltage generation circuit generates the voltages before a ready/busy signal changing from a ready state to a busy state.