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    PAGE BUFFER CIRCUIT AND MEMORY DEVICE INCLUDING THE SAME
    3.
    发明公开
    PAGE BUFFER CIRCUIT AND MEMORY DEVICE INCLUDING THE SAME 审中-公开

    公开(公告)号：US20240331776A1

    公开(公告)日：2024-10-03

    申请号：US18743852

    申请日：2024-06-14

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Yongsung CHO

    IPC: G11C16/24 ,  G11C16/26

    CPC classification number: G11C16/24 ,  G11C16/26

    Abstract: A memory device includes a memory cell array, and a page buffer circuit connected to the memory cell array through a plurality of bit lines, including a plurality of page buffers arranged in correspondence with the bit lines and each of which includes a sensing node. The plurality of page buffers include a first page buffer, and the first page buffer includes: a first sensing node configured to sense data by corresponding to a first metal wire at a lower metal layer; and a second metal wire electrically connected to the first metal wire and at an upper metal layer located above the lower metal layer, and a boost node corresponding to a third metal wire adjacent to the second metal wire of the upper metal layer and configured to control a boost-up and a boost-down of a voltage of the first sensing node.

    System and method for reliable sensing of memory cells
    5.
    发明授权
    System and method for reliable sensing of memory cells 有权

    公开(公告)号：US12106809B2

    公开(公告)日：2024-10-01

    申请号：US18362201

    申请日：2023-07-31

    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

    Inventor： Szu-Chun Tsao ,  Jaw-Juinn Horng

    IPC: G11C16/24 ,  G11C16/26

    CPC classification number: G11C16/24 ,  G11C16/26

    Abstract: Disclosed herein are related to a memory system including a memory cell and a circuit to operate the memory cell. In one aspect, the circuit includes a pair of transistors to electrically couple, to the bit line, a selected one of i) a voltage source to supply a reference voltage to the memory cell or ii) a sensor to sense a current through the memory cell. In one aspect, the circuit includes a first transistor. The first transistor and the bit line may be electrically coupled between the pair of transistors and the memory cell in series.

    MEMORY DEVICE PERFORMING SIGNED MULTIPLICATION USING LOGICAL STATES OF MEMORY CELLS
    6.
    发明公开
    MEMORY DEVICE PERFORMING SIGNED MULTIPLICATION USING LOGICAL STATES OF MEMORY CELLS 审中-公开

    公开(公告)号：US20240304252A1

    公开(公告)日：2024-09-12

    申请号：US18423161

    申请日：2024-01-25

    Applicant: Micron Technology, Inc.

    Inventor： Hernan Castro

    IPC: G11C16/10 ,  G11C16/24 ,  G11C16/26

    CPC classification number: G11C16/102 ,  G11C16/24 ,  G11C16/26

    Abstract: Systems, methods, and apparatus related to memory devices that perform signed multiplication using logical states of memory cells. In one approach, a memory device has a memory array including sets of memory cells programmed to store a signed weight in each set (e.g., four cells in a set store a signed weight of +1, 0, or −1). Voltages that represent signed inputs (e.g., +1, 0, or −1) are applied to the memory cells to perform the multiplication. A result from the multiplication is determined based on summing of output currents from the memory cells.

    SEMICONDUCTOR MEMORY DEVICE FOR PERFORMING PROGRAM OPERATION
    8.
    发明公开
    SEMICONDUCTOR MEMORY DEVICE FOR PERFORMING PROGRAM OPERATION 审中-公开

    公开(公告)号：US20240290393A1

    公开(公告)日：2024-08-29

    申请号：US18450135

    申请日：2023-08-15

    Applicant: SK hynix Inc.

    Inventor： Yeong Jo MUN ,  Kang Woo PARK

    IPC: G11C16/24

    CPC classification number: G11C16/24

    Abstract: Provided herein may be a semiconductor memory device. The semiconductor memory device may include a memory cell array including a plurality of memory cells, a plurality of page buffers respectively coupled to the plurality of memory cells through bit lines, and a control logic configured to control a program operation of each of the plurality of page buffers. Each of the plurality of page buffers may include a first latch circuit configured to store first data indicating a main verification result obtained using a main verify voltage, a second latch circuit configured to store second data indicating a first sub-verification result obtained using a first sub-verify voltage lower than the main verify voltage, and a third latch circuit configured to store third data indicating a second sub-verification result obtained using a second sub-verify voltage lower than the first sub-verify voltage.

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