公开(公告)号：US12119051B2

公开(公告)日：2024-10-15

申请号：US17884861

申请日：2022-08-10

Applicant: Micron Technology, Inc.

Inventor： Jeremy Binfet ,  Mark Helm ,  William Filipiak ,  Mark Hawes

IPC: G11C11/419 ,  G11C7/08 ,  G11C7/10 ,  G11C7/20 ,  G11C7/22 ,  G11C16/20 ,  G11C16/24 ,  G11C16/26 ,  G11C16/04

CPC classification number: G11C11/419 ,  G11C7/08 ,  G11C7/1015 ,  G11C7/1072 ,  G11C7/20 ,  G11C7/227 ,  G11C16/20 ,  G11C16/24 ,  G11C16/26 ,  G11C16/0483 ,  G11C2207/2281

Abstract: Systems, devices, and methods related to reset read are described. A reset read may be employed to initiate a transition of a portion of memory array into a first state or maintain a portion of memory array in a first state, such as a transient state. A reset read may provide a highly-parallelized, energy-efficient option to ensure memory blocks are in the first state. Various modes of reset read may be configured according to different input.

公开(公告)号：US11727972B2

公开(公告)日：2023-08-15

申请号：US17459624

申请日：2021-08-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Tsung-Hsien Huang ,  Wei-Jer Hsieh ,  Yu-Hao Hsu

IPC: G11C7/12 ,  G11C8/18 ,  H03K19/017 ,  G11C11/413 ,  G11C11/419 ,  G11C11/412 ,  G11C8/08 ,  G11C7/22

CPC classification number: G11C8/18 ,  G11C8/08 ,  G11C11/412 ,  G11C11/413 ,  G11C11/419 ,  H03K19/01742 ,  G11C7/12 ,  G11C7/227

Abstract: A memory device is disclosed. The memory device includes word lines, a tracking bit line and a word line driver. The word lines are configured to transmit word line signals to memory cells. The tracking bit line is coupled to a first plurality of tracking cells that are arranged in rows. The word line driver is coupled to the word lines and a control circuit that is coupled through the tracking bit line to the word lines. The word line driver is configured to control a falling edge of each of the word line signals, by receiving each corresponding tracking bit line signal of tracking bit line signals transmitted from the tracking bit line, based on a resistance of a length of the tracking bit line. The length is substantially distanced from each corresponding row of the rows to the control circuit. A method is also disclosed herein.

公开(公告)号：US20190198076A1

公开(公告)日：2019-06-27

申请号：US16288323

申请日：2019-02-28

Applicant: SK hynix Inc.

Inventor： Byeong Cheol LEE

IPC: G11C8/18 ,  G11C8/12 ,  G11C7/22 ,  G11C29/18 ,  G11C16/04 ,  G11C16/08 ,  G11C16/26 ,  G11C29/00 ,  G11C11/408 ,  G11C8/06 ,  G11C16/20

CPC classification number: G11C8/18 ,  G11C7/22 ,  G11C7/227 ,  G11C8/06 ,  G11C8/12 ,  G11C11/408 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/20 ,  G11C16/26 ,  G11C29/18 ,  G11C29/781 ,  G11C29/842 ,  G11C29/846

Abstract: An address control circuit may be provided. The address control circuit may include a first path circuit configured to generate a block select signal according to a control signal and an address signal. The address control circuit may include a second path circuit configured to generate, using the control signal, a dummy address signal making a transition at a timing substantially identical with a transition timing of the address signal, and generate, using the dummy address signal, an address latch signal for latching the block select signal.

公开(公告)号：US20180374524A1

公开(公告)日：2018-12-27

申请号：US15854169

申请日：2017-12-26

Applicant: SK hynix Inc.

Inventor： Byeong Cheol LEE

IPC: G11C8/18 ,  G11C16/20 ,  G11C16/26 ,  G11C16/04 ,  G11C16/08 ,  G11C29/18 ,  G11C7/22 ,  G11C8/12

CPC classification number: G11C8/18 ,  G11C7/22 ,  G11C7/227 ,  G11C8/06 ,  G11C8/12 ,  G11C11/408 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/20 ,  G11C16/26 ,  G11C29/18 ,  G11C29/781 ,  G11C29/842 ,  G11C29/846

Abstract: An address control circuit may be provided. The address control circuit may include a first path circuit configured to generate a block select signal according to a control signal and an address signal. The address control circuit may include a second path circuit configured to generate, using the control signal, a dummy address signal making a transition at a timing substantially identical with a transition timing of the address signal, and generate, using the dummy address signal, an address latch signal for latching the block select signal.

公开(公告)号：US20180294020A1

公开(公告)日：2018-10-11

申请号：US16005121

申请日：2018-06-11

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Chien-Kuo SU ,  Cheng Hung LEE ,  Chiting CHENG ,  Hung-Jen LIAO ,  Jonathan Tsung-Yung CHANG ,  Yen-Huei CHEN ,  Pankaj AGGARWAL ,  Jhon Jhy LIAW

IPC: G11C7/12 ,  G11C11/419 ,  G11C7/22

CPC classification number: G11C7/12 ,  G11C7/227 ,  G11C11/419

Abstract: A memory macro includes a first set of memory cells, a second set of memory cells and a set of conductive lines. The first set of memory cells is arranged in columns and rows. Each memory cell of the first set of memory cells includes a voltage supply node configured to receive a first voltage of a first supply voltage or a second voltage of a second supply voltage. The second set of memory cells includes a set of retention circuits configured to supply the second voltage of the second supply voltage to the first set of memory cells during a sleep operational mode. The set of conductive lines is coupled to the set of retention circuits and the voltage supply node of each memory cell of the first set of memory cells.

公开(公告)号：US20180268894A1

公开(公告)日：2018-09-20

申请号：US15462549

申请日：2017-03-17

Applicant: ARM Limited

Inventor： Jitendra Dasani ,  Vivek Nautiyal ,  Shri Sagar Dwivedi ,  Fakhruddin Ali Bohra

IPC: G11C11/419 ,  G11C11/418

CPC classification number: G11C11/419 ,  G11C7/227 ,  G11C11/418

Abstract: A memory device includes a bitcell array having a plurality of bitcells, a dummy wordline, a dummy row cell pulldown, and a write tracker coupling the dummy wordline to the dummy row cell pulldown. The write tracker is configured as a transmission gate during a read operation on the bitcell array, and is configured as having only one or more active nMOSFETs during a write operation on the bitcell array.

公开(公告)号：US09978444B2

公开(公告)日：2018-05-22

申请号：US15077636

申请日：2016-03-22

Applicant: QUALCOMM Incorporated

Inventor： Tony Chung Yiu Kwok ,  Changho Jung

IPC: G11C11/00 ,  G11C11/419 ,  G11C7/08 ,  G11C7/22 ,  G11C8/18 ,  G11C7/10

CPC classification number: G11C11/419 ,  G11C7/08 ,  G11C7/1039 ,  G11C7/1042 ,  G11C7/227 ,  G11C8/18 ,  G11C2207/2209 ,  G11C2207/2281 ,  G11C2207/229

Abstract: A memory and a method for operating the memory are presented. The memory includes a memory cell, a sense amplifier configured to sense read data from the memory cell, a write driver configured to provide write data to the memory cell, a first circuit configured to enable the sense amplifier during a time period, and a second circuit configured to enable the write driver during at least a portion of the time period. The method includes enabling a sense amplifier to sense read data from a memory cell during a time period and enabling a write driver to provide write data to the memory cell during at least a portion of the time period. Another memory and method for operating the memory are presented. The memory and method further include an address input circuit configured to receive a write address while the sense amplifier is enabled.

公开(公告)号：US09978442B2

公开(公告)日：2018-05-22

申请号：US15258964

申请日：2016-09-07

Applicant: QUALCOMM Incorporated

Inventor： Bin Liang ,  Tony Chung Yiu Kwok ,  Rui Li ,  Sei Seung Yoon

IPC: G11C11/4076 ,  G11C7/14 ,  G11C11/418 ,  G11C11/419 ,  G11C7/10 ,  G11C13/00

CPC classification number: G11C11/418 ,  G11C7/1072 ,  G11C7/227 ,  G11C8/18 ,  G11C11/419 ,  G11C13/0061

Abstract: A memory is disclosed. The memory includes a memory array having a plurality of memory cells. The memory also includes an address decoder configured to assert a wordline to enable the memory cells. Additionally, the memory includes a tracking circuit configured to vary a duration of asserting the wordline as a function of which one of the memory cells is accessed. A method is also disclosed. The method includes asserting a wordline to enable the memory cells and varying a duration of asserting the wordline as a function of which one of a plurality of memory cells is accessed.

公开(公告)号：US20180053537A1

公开(公告)日：2018-02-22

申请号：US15798710

申请日：2017-10-31

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Chien-Kuo SU ,  Cheng Hung LEE ,  Chiting CHENG ,  Hung-Jen LIAO ,  Jonathan Tsung-Yung CHANG ,  Yen-Huei CHEN ,  Pankaj AGGARWAL ,  Jhon Jhy LIAW

IPC: G11C7/12

CPC classification number: G11C7/12 ,  G11C7/227 ,  G11C11/419

Abstract: A memory macro includes a first set of memory cells, a second set of memory cells, a third set of memory cells, a set of retention circuits and a set of conductive lines. The second set of memory cells arranged in a first row arranged in a second direction. The third set of memory cells arranged in a first column arranged in a first direction. The set of retention circuits is configured to supply a second voltage value of a second supply voltage to the first set of memory cells during a sleep operational mode. The set of retention circuits is responsive to a set of control signals, and arranged in a second column arranged in the first direction. The set of conductive lines extend in the second direction, and coupled to the set of retention circuits and the voltage supply node of the first set of memory cells.

公开(公告)号：US09875782B2

公开(公告)日：2018-01-23

申请号：US15401871

申请日：2017-01-09

Applicant: SK hynix Inc. ,  Industry-Academic Cooperation Foundation, Yonsei University

Inventor： Kangwook Jo ,  Jongil Hong ,  Hongil Yoon

IPC: G11C11/00 ,  G11C11/16

CPC classification number: G11C11/1675 ,  G11C7/227 ,  G11C11/161 ,  G11C11/1655 ,  G11C11/1657 ,  G11C11/1697

Abstract: A magnetic memory device may include a bit line, a plurality of source lines, a plurality of normal cells coupled between the bit line and the plurality of source lines, and each including a magnetic resistance element and a switching element coupled in series to the magnetic resistance element and switched by a word line signal, a dummy cell coupled to the bit line, and a spin-hall effect material layer between the bit line and the magnetic resistance element. The magnetic resistance element may write data according to a first current that flows through the dummy cell and flows in a direction parallel to the magnetic resistance element, and a second current that flows through the magnetic resistance element.