公开(公告)号：US20190220222A1

公开(公告)日：2019-07-18

申请号：US16329051

申请日：2017-07-07

申请人： Rambus Inc.

发明人： Frederick A. Ware ,  John Eric Linstadt ,  Torsten Partsch

IPC分类号： G06F3/06 ,  G11C7/10 ,  G11C7/06 ,  G11C7/22 ,  H01L25/065 ,  G06F13/16

CPC分类号： G06F3/0655 ,  G06F3/0604 ,  G06F3/0679 ,  G06F13/1668 ,  G06F2213/16 ,  G11C7/06 ,  G11C7/1015 ,  G11C7/1057 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/1087 ,  G11C7/1093 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/4096 ,  G11C2207/107 ,  G11C2207/2272 ,  G11C2207/2281 ,  G11C2207/229 ,  H01L25/0657 ,  H01L2225/06541

摘要： First data is read out of a core storage array of a memory component over a first time interval constrained by data output bandwidth of the core storage array. After read out from the core storage array, the first data is output from the memory component over a second time interval that is shorter than the first time interval and that corresponds to a data transfer bandwidth greater than the data output bandwidth of the core storage array.

公开(公告)号：US20180308528A1

公开(公告)日：2018-10-25

申请号：US16004122

申请日：2018-06-08

申请人： Micron Technology, Inc.

发明人： Timothy P. Finkbeiner ,  Glen E. Hush ,  David L. Pinney

IPC分类号： G11C7/06 ,  G11C11/4096 ,  G11C11/4094 ,  G11C11/4091 ,  G11C7/10 ,  G11C7/22 ,  G11C11/4076

CPC分类号： G11C7/065 ,  G11C7/1006 ,  G11C7/1012 ,  G11C7/106 ,  G11C7/1087 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4096 ,  G11C2207/229 ,  G11C2211/4013

摘要： The present disclosure includes apparatuses and methods related to accessing data in memory. One example method comprises storing data associated with a first operation in a first sense amplifier responsive to receiving a request to perform a second operation, and performing the second operation associated with a row of memory cells while the data associated with the first operation is being stored in the first sense amplifier.

公开(公告)号：US20180211696A1

公开(公告)日：2018-07-26

申请号：US15653842

申请日：2017-07-19

申请人： SK hynix Inc.

发明人： Soojin KIM ,  Sangwon LEE

IPC分类号： G11C7/10 ,  G11C11/419 ,  G11C11/407 ,  G11C11/418

CPC分类号： G11C7/1051 ,  G06F11/1048 ,  G06F13/16 ,  G11C7/1072 ,  G11C7/1087 ,  G11C7/22 ,  G11C11/1675 ,  G11C11/407 ,  G11C11/418 ,  G11C11/419 ,  G11C13/0069 ,  G11C16/10 ,  G11C2207/2245 ,  G11C2207/229

摘要： A semiconductor system includes a controller. The controller is configured to have a write buffer that stores first write data outputted from a host before the first write data is written into a memory circuit. The controller is configured to write the first write data stored in the write buffer into the memory circuit under a first condition and configured to double-write the first write data stored in the write buffer into the memory circuit under a second condition.

公开(公告)号：US20180189133A1

公开(公告)日：2018-07-05

申请号：US15653749

申请日：2017-07-19

申请人： TEXAS INSTRUMENTS INCORPORATED

发明人： Indu PRATHAPAN ,  Prashanth SARAF ,  Desmond Pravin Martin FERNANDES ,  Saket JALAN

IPC分类号： G06F11/10 ,  G11C5/04 ,  G06F3/06 ,  G11C11/16 ,  G11C11/56 ,  H03M13/35

CPC分类号： G06F11/1044 ,  G06F3/0653 ,  G06F11/1012 ,  G06F11/1068 ,  G06F11/1076 ,  G06F11/108 ,  G11C5/04 ,  G11C7/1006 ,  G11C7/22 ,  G11C11/1675 ,  G11C11/5628 ,  G11C2207/2263 ,  G11C2207/229 ,  H03M13/19 ,  H03M13/35 ,  H03M13/356 ,  H03M13/3776

摘要： In the described examples, a memory controller includes a read-modify-write logic module that receives a partial write data request for partial write data in error-correcting code (ECC) memory and combines the partial write data in the partial write data request with read data provided from the ECC memory to form combined data prior to correcting the read data. The memory controller also includes a write control module that controls the writing of the combined data to the ECC memory.

公开(公告)号：US10014069B2

公开(公告)日：2018-07-03

申请号：US15597382

申请日：2017-05-17

申请人： SK hynix Inc.

发明人： Min Su Park

IPC分类号： G11C29/00 ,  G11C11/406 ,  G11C11/4096 ,  G11C11/408 ,  G11C7/24 ,  G11C7/02 ,  G11C11/4076 ,  G11C8/08

CPC分类号： G11C29/00 ,  G11C7/02 ,  G11C7/24 ,  G11C8/08 ,  G11C11/40603 ,  G11C11/40615 ,  G11C11/40622 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4085 ,  G11C11/4096 ,  G11C29/808 ,  G11C2207/2281 ,  G11C2207/229

摘要： There may be provided a memory or memory system. A memory may include an active cell array comprising a plurality of unit cells coupled to a word line and configured to store an active count of the word line. The memory may include a read control circuit configured to read the active count of the word line from the active cell array. The memory may be configured to refresh an adjacent word line of the corresponding word line based on the active count of the word line.

公开(公告)号：US09997212B1

公开(公告)日：2018-06-12

申请号：US15494879

申请日：2017-04-24

申请人： Micron Technology, Inc.

发明人： Timothy P. Finkbeiner ,  Glen E. Hush ,  David L. Pinney

IPC分类号： G11C7/02 ,  G11C7/06 ,  G11C7/22 ,  G11C8/10

CPC分类号： G11C7/065 ,  G11C7/1006 ,  G11C7/1012 ,  G11C7/106 ,  G11C7/1087 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4096 ,  G11C2207/229 ,  G11C2211/4013

摘要： The present disclosure includes apparatuses and methods related to accessing data in memory. One example method comprises storing data associated with a first operation in a first sense amplifier responsive to receiving a request to perform a second operation, and performing the second operation associated with a row of memory cells while the data associated with the first operation is being stored in the first sense amplifier.

公开(公告)号：US20170329534A1

公开(公告)日：2017-11-16

申请号：US15667358

申请日：2017-08-02

申请人： Micron Technology, Inc.

发明人： Graziano Mirichigni ,  Daniele Balluchi ,  Luca Porzio

IPC分类号： G06F3/06

CPC分类号： G06F13/1689 ,  G06F13/161 ,  G11C7/106 ,  G11C7/1063 ,  G11C7/22 ,  G11C8/06 ,  G11C2207/2209 ,  G11C2207/2272 ,  G11C2207/229

摘要： Apparatuses and methods for variable latency memory operations are disclosed herein. An example apparatus may include a memory configured to provide first information during a variable latency period indicating the memory is not available to perform a command, wherein the first information is indicative of a remaining length of the variable latency period, the remaining length is one of a relatively short, normal, or long period of time, the memory configured to provide second information in response to receiving the command after the latency period.

公开(公告)号：US20170076766A1

公开(公告)日：2017-03-16

申请号：US14978733

申请日：2015-12-22

申请人： Cypress Semiconductor Corporation

发明人： Vineet Agrawal ,  Roger Bettman ,  Samuel Leshner

IPC分类号： G11C7/18 ,  G11C5/14 ,  G11C7/12 ,  G11C7/22 ,  G06F12/02 ,  G11C7/06

CPC分类号： G11C7/18 ,  G06F12/023 ,  G06F2212/1044 ,  G11C5/147 ,  G11C7/06 ,  G11C7/1015 ,  G11C7/12 ,  G11C7/22 ,  G11C2207/2209 ,  G11C2207/2281 ,  G11C2207/229

摘要： Disclosed herein are systems, methods, and devices for parallel read and write operations. Devices may include a first transmission device coupled to a local bit line and a global bit line associated with a memory unit of a memory array. The first transmission device may be configured to selectively couple the global bit line to the local bit line. The devices may further include a first device coupled to the local bit line and a sense amplifier. The first device may be configured to selectively couple the local bit line to the sense amplifier. The devices may also include a second device coupled to the local bit line and an electrical ground. The second device may be configured to selectively couple the local bit line to the electrical ground.

摘要翻译： 这里公开了用于并行读写操作的系统，方法和装置。 设备可以包括耦合到本地位线的第一传输设备和与存储器阵列的存储器单元相关联的全局位线。 第一传输设备可以被配置为选择性地将全局位线耦合到本地位线。 器件还可以包括耦合到本地位线的第一器件和读出放大器。 第一器件可以被配置为选择性地将局部位线耦合到读出放大器。 该装置还可以包括耦合到本地位线和电接地的第二装置。 第二装置可以被配置为选择性地将局部位线耦合到电接地。

公开(公告)号：US09411727B2

公开(公告)日：2016-08-09

申请号：US14963201

申请日：2015-12-08

申请人： QUALCOMM INCORPORATED

发明人： Xiangyu Dong ,  Xiaochun Zhu ,  Jungwon Suh

IPC分类号： G06F12/08 ,  G11C7/10 ,  G11C11/16 ,  G06F13/00

CPC分类号： G06F12/0802 ,  G06F12/08 ,  G06F12/0855 ,  G06F12/0864 ,  G06F2212/1016 ,  G06F2212/22 ,  G06F2212/222 ,  G06F2212/60 ,  G11C7/1015 ,  G11C7/1039 ,  G11C7/1084 ,  G11C11/165 ,  G11C11/1653 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/1693 ,  G11C13/0002 ,  G11C2207/2245 ,  G11C2207/2272 ,  G11C2207/2281 ,  G11C2207/229

摘要： A method of reading from and writing to a resistive memory cache includes receiving a write command and dividing the write command into multiple write sub-commands. The method also includes receiving a read command and executing the read command before executing a next write sub-command.

摘要翻译： 读取和写入电阻式存储器高速缓存的方法包括接收写入命令并将写入命令分成多个写入子命令。 该方法还包括在执行下一个写入子命令之前接收读取命令并执行读取命令。

公开(公告)号：US20160191031A1

公开(公告)日：2016-06-30

申请号：US15065952

申请日：2016-03-10

申请人： Apple Inc.

发明人： Ajay Kumar Bhatia

IPC分类号： H03K5/134 ,  G06F1/08 ,  G06F1/26

CPC分类号： H03K5/134 ,  G01R19/0084 ,  G01R31/40 ,  G06F1/08 ,  G06F1/24 ,  G06F1/26 ,  G06F1/305 ,  G11C5/14 ,  G11C7/1066 ,  G11C7/1093 ,  G11C7/222 ,  G11C2207/2281 ,  G11C2207/229 ,  H03K5/13 ,  H03K5/133 ,  H03K19/00369 ,  H03K2005/00019 ,  H03K2005/00039

摘要： Embodiments of a method that may allow for selectively tuning a delay of individual logic paths within a custom circuit or memory are disclosed. Circuitry may be configured to monitor a voltage level of a power supply coupled to the custom circuit or memory. A delay amount of a delay unit within the custom circuit or memory may be changed in response to a determination that the voltage level of the power supply has changed.