公开(公告)号：US20180041222A1

公开(公告)日：2018-02-08

申请号：US15782052

申请日：2017-10-12

申请人： Texas Instruments Incorporated

发明人： Sundarrajan RANGACHARI ,  Desmond Pravin Martin FERNANDES ,  Rakesh Channabasappa Yaraduyathinahalli

IPC分类号： H03M7/30

CPC分类号： H03M7/30 ,  G06F3/06 ,  G06F13/00 ,  G06F2212/401 ,  H03M7/6047

摘要： Disclosed embodiments include a system having a first memory for storing a plurality of data quantities, each data quantity consisting of a first number of bits, and a second memory for storing a plurality of compressed data quantities, each compressed data quantity consisting of a second number of bits that is less than the first number of bits. The system includes circuitry for reading data quantities from the first memory and for writing compressed data quantities, corresponding to respective read data quantities, to non-sequential addresses in the second memory. The circuitry for reading data quantities from the first memory is for reading along a read orientation selected from one of row-orientation or column-orientation from the first memory, and the circuitry for writing compressed data quantities in the second memory is for writing along a write orientation in the second memory that differs from the read orientation.

公开(公告)号：US20180189133A1

公开(公告)日：2018-07-05

申请号：US15653749

申请日：2017-07-19

申请人： TEXAS INSTRUMENTS INCORPORATED

发明人： Indu PRATHAPAN ,  Prashanth SARAF ,  Desmond Pravin Martin FERNANDES ,  Saket JALAN

IPC分类号： G06F11/10 ,  G11C5/04 ,  G06F3/06 ,  G11C11/16 ,  G11C11/56 ,  H03M13/35

CPC分类号： G06F11/1044 ,  G06F3/0653 ,  G06F11/1012 ,  G06F11/1068 ,  G06F11/1076 ,  G06F11/108 ,  G11C5/04 ,  G11C7/1006 ,  G11C7/22 ,  G11C11/1675 ,  G11C11/5628 ,  G11C2207/2263 ,  G11C2207/229 ,  H03M13/19 ,  H03M13/35 ,  H03M13/356 ,  H03M13/3776

摘要： In the described examples, a memory controller includes a read-modify-write logic module that receives a partial write data request for partial write data in error-correcting code (ECC) memory and combines the partial write data in the partial write data request with read data provided from the ECC memory to form combined data prior to correcting the read data. The memory controller also includes a write control module that controls the writing of the combined data to the ECC memory.

公开(公告)号：US20180175880A1

公开(公告)日：2018-06-21

申请号：US15895721

申请日：2018-02-13

申请人： Texas Instruments Incorporated

发明人： Sundarrajan RANGACHARI ,  Desmond Pravin Martin FERNANDES ,  Rakesh Channabasappa Yaraduyathinahalli

IPC分类号： H03M7/30

CPC分类号： H03M7/30 ,  G06F3/06 ,  G06F13/00 ,  G06F2212/401 ,  H03M7/6047

摘要： Disclosed embodiments include a system having a first memory, a second memory, circuitry that reads data quantities from the first memory along a first orientation, a compression engine that compresses each of the read data quantities to produce corresponding compressed data quantities, and circuitry that writes the compressed data quantities to the second memory along a second orientation which differs from the first orientation. The read data quantities have a first bit width and the compressed data quantities have a second bit width that is less than the first bit width.