公开(公告)号：US10741229B2

公开(公告)日：2020-08-11

申请号：US16119285

申请日：2018-08-31

申请人： Sk hynix Inc.

发明人： Min Su Park ,  Dong Kyun Kim

IPC分类号： G11C7/22 ,  G11C7/10 ,  G11C19/28

摘要： A semiconductor device may include an internal command pulse generation circuit and a sense data generation circuit. The internal command pulse generation circuit may generate an internal command pulse from a write signal based on an offset code and an internal clock signal. The sense data generation circuit may generate sense data from an internal data strobe signal based on the internal command pulse. The internal command pulse may be generated by delaying the write signal by a shift period based on the internal clock signal. The shift period may be controlled by the offset code.

公开(公告)号：US10014069B2

公开(公告)日：2018-07-03

申请号：US15597382

申请日：2017-05-17

申请人： SK hynix Inc.

发明人： Min Su Park

IPC分类号： G11C29/00 ,  G11C11/406 ,  G11C11/4096 ,  G11C11/408 ,  G11C7/24 ,  G11C7/02 ,  G11C11/4076 ,  G11C8/08

CPC分类号： G11C29/00 ,  G11C7/02 ,  G11C7/24 ,  G11C8/08 ,  G11C11/40603 ,  G11C11/40615 ,  G11C11/40622 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4085 ,  G11C11/4096 ,  G11C29/808 ,  G11C2207/2281 ,  G11C2207/229

摘要： There may be provided a memory or memory system. A memory may include an active cell array comprising a plurality of unit cells coupled to a word line and configured to store an active count of the word line. The memory may include a read control circuit configured to read the active count of the word line from the active cell array. The memory may be configured to refresh an adjacent word line of the corresponding word line based on the active count of the word line.

公开(公告)号：US09858142B2

公开(公告)日：2018-01-02

申请号：US15062557

申请日：2016-03-07

申请人： SK hynix Inc.

发明人： Min Su Park

IPC分类号： G06F11/10 ,  G11C11/406 ,  G11C11/408 ,  H03M13/00

CPC分类号： G06F11/1044 ,  G11C11/406 ,  G11C11/4082 ,  G11C11/4085 ,  G11C29/1201 ,  G11C29/12015 ,  G11C29/20 ,  G11C29/44 ,  G11C29/50016 ,  G11C29/52 ,  G11C29/76 ,  G11C29/783 ,  G11C29/789 ,  G11C2029/0409 ,  G11C2029/0411 ,  G11C2211/4062 ,  H03M13/6566

摘要： Provided is a semiconductor device including an error correction code circuit. The semiconductor device includes a bank including a memory area for storing data and an error correction for storing parity data, an error correction code calculation circuit that corrects an error of a failed cell in correspondence to the data and the parity data and outputs a flag signal activated at a time of a generation of failed data and an address activated in the bank, an address latch circuit that stores the address applied from the error correction code calculation circuit and outputs a failed address according to the flag signal, and a fail prevention circuit that performs an operation for repairing the failed data in correspondence to the flag signal and the failed address.

公开(公告)号：US09741422B1

公开(公告)日：2017-08-22

申请号：US15170554

申请日：2016-06-01

申请人： SK hynix Inc.

发明人： Min Su Park ,  Jae Il Kim

IPC分类号： G11C7/00 ,  G11C11/406 ,  G11C11/408 ,  G11C7/22 ,  G11C7/10

CPC分类号： G11C11/40618 ,  G11C7/1051 ,  G11C7/1078 ,  G11C7/109 ,  G11C7/22 ,  G11C11/40611 ,  G11C11/4076 ,  G11C11/4082 ,  G11C11/4087 ,  G11C11/4096

摘要： A refresh control device may include a plurality of latch circuits configured to receive an active signal, a refresh signal, an active control signal, and a refresh control signal, and output a word line enable signal for controlling a refresh operation to banks. The refresh control device may include a command decoder configured to decode a row address in correspondence to an external command signal and generate the active signal and the refresh signal. The refresh control device may include an address buffer configured to buffer an active address and generate the active control signal. The refresh control device may include an address control circuit configured to generate the refresh control signal in correspondence to a refresh command signal.

公开(公告)号：US09397039B2

公开(公告)日：2016-07-19

申请号：US14148068

申请日：2014-01-06

申请人： SK hynix Inc.

发明人： Min Su Park

IPC分类号： H01L23/522 ,  H01L23/528

CPC分类号： H01L23/5226 ,  H01L23/522 ,  H01L23/5286 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes: a second conductive layer formed over a first conductive layer; and a dummy conductive layer formed between the first and second conductive layers with through-holes formed therein. The first and second conductive layers include signal lines electrically coupled to each other through signal metal contacts passing through the through-holes, and the second conductive layer includes power lines electrically coupled to the dummy conductive layer through power metal contacts.

摘要翻译： 半导体器件包括：形成在第一导电层上的第二导电层; 以及在第一导电层和第二导电层之间形成有通孔的虚设导电层。 第一和第二导电层包括通过穿过通孔的信号金属触点彼此电耦合的信号线，并且第二导电层包括通过功率金属触点电耦合到虚设导电层的电力线。

公开(公告)号：US11249680B2

公开(公告)日：2022-02-15

申请号：US16584417

申请日：2019-09-26

申请人： SK hynix Inc.

发明人： Min Su Park ,  Dong Kyun Kim ,  Sang Sic Yoon

IPC分类号： G06F3/00 ,  G06F3/06 ,  G11C7/22 ,  G11C7/10

摘要： A semiconductor system includes a semiconductor device and a controller. The semiconductor device includes a first memory rank and is configured to perform, in response to receiving a first write command, a first write operation of writing first data to the first memory rank. The semiconductor device includes a second memory rank and is configured to perform, in response to receiving a second write command, a second write operation of writing second data to the second memory rank. The controller is configured to receive at least one write request and responsively generate the first and second write commands separated in time so that a transition time interval between generation of the first write command and generation of the second write command is based on the second memory rank being different from the first memory rank and based on a comparison of a write preamble period to a write post-amble period.

公开(公告)号：US10658015B2

公开(公告)日：2020-05-19

申请号：US16212545

申请日：2018-12-06

申请人： SK hynix Inc.

发明人： Geun Ho Choi ,  Min Su Park ,  Sun Myung Choi

IPC分类号： G11C7/10 ,  G11C11/4076 ,  G11C7/22 ,  G11C11/409

摘要： A semiconductor device includes a shift register and a control signal generation circuit. The shift register generates shifted pulses, wherein a number of the shifted pulses is controlled according to a mode of a burst length. The control signal generation circuit generates a control signal for setting a burst operation period according to a period during which the shifted pulses are created. The burst operation period is a period during which a burst operation is performed.

公开(公告)号：US10282289B2

公开(公告)日：2019-05-07

申请号：US15862730

申请日：2018-01-05

申请人： SK hynix Inc.

发明人： Hak Song Kim ,  Min Su Park

IPC分类号： G11C7/00 ,  G06F12/02 ,  G06F3/06 ,  G11C7/10 ,  G11C16/26 ,  G11C5/02 ,  G11C16/04

摘要： A package module may be provided. The package module may include a first chip and a second chip. The first chip may be configured to receive first pattern data to generate first transmission data in a first write mode. The second chip may be configured to receive the first transmission data to generate and output first sense data in a first read mode.

公开(公告)号：US09959922B2

公开(公告)日：2018-05-01

申请号：US15689893

申请日：2017-08-29

申请人： SK hynix Inc.

发明人： Min Su Park

IPC分类号： G11C7/10 ,  G11C11/408 ,  G11C11/406 ,  G11C11/4094 ,  G11C11/4091 ,  G11C11/4093

CPC分类号： G11C11/4085 ,  G11C11/406 ,  G11C11/40603 ,  G11C11/40618 ,  G11C11/4087 ,  G11C11/4091 ,  G11C11/4093 ,  G11C11/4094

摘要： A semiconductor system includes a first semiconductor device and a second semiconductor device. The first semiconductor device outputs a command/address signal. The second semiconductor device extracts an active signal, a pre-charge signal, and addresses from the command/address signal, performs an active operation on a memory cell corresponding to the addresses, and performs a refresh operation on the memory cell corresponding to counting signals generated by counting a number of pulses in a refresh signal.

公开(公告)号：US09779799B2

公开(公告)日：2017-10-03

申请号：US14925353

申请日：2015-10-28

申请人： SK hynix Inc.

发明人： Min Su Park

IPC分类号： G11C7/10 ,  G11C11/408 ,  G11C11/406 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4093

CPC分类号： G11C11/4085 ,  G11C11/406 ,  G11C11/40603 ,  G11C11/40618 ,  G11C11/4087 ,  G11C11/4091 ,  G11C11/4093 ,  G11C11/4094

摘要： A semiconductor system includes a first semiconductor device and a second semiconductor device. The first semiconductor device outputs a command/address signal. The second semiconductor device extracts an active signal, a pre-charge signal, and addresses from the command/address signal, performs an active operation on a memory cell corresponding to the addresses, and performs a refresh operation on the memory cell corresponding to counting signals generated by counting a number of pulses in a refresh signal.