公开(公告)号：US20240070069A1

公开(公告)日：2024-02-29

申请号：US18215474

申请日：2023-06-28

申请人： Micron Technology, Inc.

发明人： Brent Keeth ,  Owen Fay ,  Chan H. Yoo ,  Roy E. Greeff ,  Matthew B. Leslie

IPC分类号： G06F12/06 ,  G06F12/02 ,  G11C11/4093 ,  G11C29/12 ,  H01L25/065 ,  H01L25/18

CPC分类号： G06F12/0653 ,  G06F12/0215 ,  G11C11/4093 ,  G11C29/12 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/18 ,  G06F2212/1016 ,  G11C2211/4062 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06541 ,  H01L2225/06562 ,  H01L2225/06586

摘要： Apparatus and methods are disclosed, including memory devices and systems. Example memory devices, systems and methods include a buffer interface to translate high speed data interactions on a host interface side into slower, wider data interactions on a DRAM interface side. The slower, and wider DRAM interface may be configured to substantially match the capacity of the narrower, higher speed host interface. In some examples, the buffer interface may be configured to provide multiple sub-channel interfaces each coupled to one or more regions within the memory structure and configured to facilitate data recovery in the event of a failure of some portion of the memory structure. Selected example memory devices, systems and methods include an individual DRAM die, or one or more stacks of DRAM dies coupled to a buffer die.

公开(公告)号：US11868650B2

公开(公告)日：2024-01-09

申请号：US17662993

申请日：2022-05-11

申请人： Micron Technology, Inc.

发明人： Hyun Yoo Lee ,  Kang-Yong Kim

IPC分类号： G06F3/00 ,  G06F3/06 ,  G11C11/406 ,  G11C11/408 ,  G11C11/4096

CPC分类号： G06F3/0655 ,  G06F3/0604 ,  G06F3/0679 ,  G11C11/406 ,  G11C11/4082 ,  G11C11/4096 ,  G11C2211/4062

摘要： Methods, apparatuses, and systems related to combining and utilizing multiple memory circuits having complementary characteristics are described. An apparatus may include a first memory circuit having a first emphasized characteristic and a second memory circuit having a second emphasized characteristic. The first and second memory circuits may be connected in parallel and to a common interface configured to communicate data between the apparatus and an external device.

公开(公告)号：US11868253B2

公开(公告)日：2024-01-09

申请号：US17861627

申请日：2022-07-11

申请人： Lodestar Licensing Group, LLC

发明人： Brent Keeth ,  Owen Fay ,  Chan H. Yoo ,  Roy E. Greeff ,  Matthew B. Leslie

IPC分类号： G11C11/00 ,  G06F12/06 ,  G11C29/12 ,  G11C11/4093 ,  H01L25/18 ,  H01L25/065 ,  G06F12/02

CPC分类号： G06F12/0653 ,  G06F12/0215 ,  G11C11/4093 ,  G11C29/12 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/18 ,  G06F2212/1016 ,  G11C2211/4062 ,  H01L2225/0651 ,  H01L2225/0652 ,  H01L2225/06506 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06562 ,  H01L2225/06586

摘要： Memory devices, systems and methods include a buffer interface to translate high speed data interactions on a host interface side into slower, wider data interactions on a DRAM interface side. The slower, and wider DRAM interface may be configured to substantially match the capacity of the narrower, higher speed host interface. In some configurations, the buffer interface may be configured to provide multiple sub-channel interfaces each coupled to one or more regions within the memory structure and configured to facilitate data recovery in the event of a failure of some portion of the memory structure. Selected memory devices, systems and methods include an individual DRAM die, or one or more stacks of DRAM dies coupled to a buffer die.

公开(公告)号：US09858142B2

公开(公告)日：2018-01-02

申请号：US15062557

申请日：2016-03-07

申请人： SK hynix Inc.

发明人： Min Su Park

IPC分类号： G06F11/10 ,  G11C11/406 ,  G11C11/408 ,  H03M13/00

CPC分类号： G06F11/1044 ,  G11C11/406 ,  G11C11/4082 ,  G11C11/4085 ,  G11C29/1201 ,  G11C29/12015 ,  G11C29/20 ,  G11C29/44 ,  G11C29/50016 ,  G11C29/52 ,  G11C29/76 ,  G11C29/783 ,  G11C29/789 ,  G11C2029/0409 ,  G11C2029/0411 ,  G11C2211/4062 ,  H03M13/6566

摘要： Provided is a semiconductor device including an error correction code circuit. The semiconductor device includes a bank including a memory area for storing data and an error correction for storing parity data, an error correction code calculation circuit that corrects an error of a failed cell in correspondence to the data and the parity data and outputs a flag signal activated at a time of a generation of failed data and an address activated in the bank, an address latch circuit that stores the address applied from the error correction code calculation circuit and outputs a failed address according to the flag signal, and a fail prevention circuit that performs an operation for repairing the failed data in correspondence to the flag signal and the failed address.

公开(公告)号：US20170161143A1

公开(公告)日：2017-06-08

申请号：US14963035

申请日：2015-12-08

申请人： Nvidia Corporation

发明人： David REED ,  Alok GUPTA

IPC分类号： G06F11/10 ,  G06F3/06 ,  G11C29/52

CPC分类号： G06F11/1068 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0659 ,  G06F3/0688 ,  G06F11/106 ,  G11C7/02 ,  G11C11/40615 ,  G11C11/4082 ,  G11C11/4087 ,  G11C11/4093 ,  G11C29/04 ,  G11C2029/0409 ,  G11C2029/0411 ,  G11C2029/4402 ,  G11C2211/4062

摘要： A method for updating a DRAM memory array is disclosed. The method comprises: a) transitioning the DRAM memory array from an idle state to a refresh state in accordance with a command from a memory controller; b) initiating a refresh on the DRAM memory array using DRAM internal control circuitry by activating a row of data into an associated sense amplifier buffer; and c) during the refresh, performing an ERR Correction Code (ECC) scrub operation of selected bits in the activated row of the DRAM memory array.

公开(公告)号：US20170069398A1

公开(公告)日：2017-03-09

申请号：US15066633

申请日：2016-03-10

申请人： SK hynix Inc.

发明人： Min-Su PARK ,  Jae-Il KIM

IPC分类号： G11C29/52 ,  G11C11/406

CPC分类号： G11C29/52 ,  G11C11/406 ,  G11C29/50016 ,  G11C2211/4062

摘要： A memory device may include a plurality of memory cells; and an error detection unit suitable for latching first read data of one or more memory cells selected from the plurality of memory cells after refreshing the selected memory cells, in a first phase, and suitable for detecting errors of the selected memory cells before refreshing the selected memory cells, in a second phase.

摘要翻译： 存储器件可以包括多个存储器单元; 以及错误检测单元，其适于在第一阶段中锁存从所述多个存储器单元中选择的一个或多个存储器单元的第一读取数据，所述第一读取数据在刷新所选择的存储器单元之后，并且适于在刷新所选择的存储单元之前检测所选存储单元的错误 存储单元，在第二阶段。

公开(公告)号：US09514800B1

公开(公告)日：2016-12-06

申请号：US15081849

申请日：2016-03-26

申请人： Bo Liu

发明人： Bo Liu

IPC分类号： G11C7/00 ,  G11C11/406 ,  G11C11/4096 ,  G11C29/44 ,  G11C29/02 ,  G11C11/4076 ,  G11C8/18 ,  G11C11/4074

CPC分类号： G11C11/40615 ,  G11C7/1006 ,  G11C8/18 ,  G11C11/406 ,  G11C11/40603 ,  G11C11/40618 ,  G11C11/4074 ,  G11C11/4076 ,  G11C11/4096 ,  G11C29/02 ,  G11C29/44 ,  G11C2211/4062

摘要： A dynamic random access memory (DRAM) with code bit and self-refresh operation is disclosed. In one particular exemplary embodiment, at least one code bit is appended to N bits of user data to form a new code data. The user data are stored in a plurality of user data sub-arrays and code bit is stored in code bit sub-array respectively. Each sub-array stores at least one bit per user-specified row and column address. Each sub-array is independently controlled in either refresh operation or user operation.Refresh operation works on at least one sub-array at a time out of a plurality of sub-arrays. User operations work on other sub-arrays out of a plurality of sub-arrays. User read operation and internal refresh operation can work concurrently.

摘要翻译： 刷新操作对多个子阵列中的一次的至少一个子阵列起作用。 用户操作对多个子阵列中的其他子阵列起作用。 用户读取操作和内部刷新操作可以同时工作。

公开(公告)号：US09472261B1

公开(公告)日：2016-10-18

申请号：US14690204

申请日：2015-04-17

申请人： QUALCOMM Incorporated

发明人： Dexter Tamio Chun ,  Jung Pill Kim ,  Yanru Li

IPC分类号： G11C5/00 ,  G11C7/00 ,  G11C29/00 ,  G11C7/04 ,  G11C11/406 ,  G11C11/4096 ,  G11C29/42 ,  G11C29/36

CPC分类号： G11C11/40626 ,  G11C7/1006 ,  G11C11/4076 ,  G11C11/4096 ,  G11C29/023 ,  G11C29/028 ,  G11C29/36 ,  G11C29/42 ,  G11C29/50016 ,  G11C2207/2245 ,  G11C2211/4062

摘要： A system and method of refreshing dynamic random access memory (DRAM) are disclosed. A device includes a DRAM, a bus, and a system-on-chip (SOC) coupled via the bus to the DRAM. The SOC is configured to refresh the DRAM at a particular refresh rate based on a temperature of the DRAM and based on calibration data determined based on one or more calibration tests performed while the SOC is coupled to the DRAM.

摘要翻译： 公开了一种刷新动态随机存取存储器（DRAM）的系统和方法。 一种器件包括通过总线耦合到DRAM的DRAM，总线和片上系统（SOC）。 SOC被配置为基于DRAM的温度以基于在SOC耦合到DRAM时执行的一个或多个校准测试确定的校准数据以特定刷新速率刷新DRAM。

公开(公告)号：US09286161B2

公开(公告)日：2016-03-15

申请号：US14464865

申请日：2014-08-21

申请人： MICRON TECHNOLOGY, INC.

发明人： J. Thomas Pawlowski

IPC分类号： G11C29/00 ,  H03M13/00 ,  G06F11/10 ,  G11C11/406 ,  G11C29/52 ,  G11C29/04

CPC分类号： G06F11/1076 ,  G06F11/1008 ,  G06F11/1044 ,  G11C11/406 ,  G11C11/40618 ,  G11C11/40622 ,  G11C29/52 ,  G11C2029/0411 ,  G11C2211/4062 ,  G11C2211/4067

摘要： A DRAM memory device includes several banks of memory cells each of which are divided into first and second sets of memory cells. The memory cells in the first set can be refreshed at a relatively slow rate to reduce the power consumed by the DRAM device. Error checking and correcting circuitry in the DRAM device corrects any data retention errors in the first set of memory cells caused by the relatively slow refresh rate. The memory cells in the second set are refreshed at a normal rate, which is fast enough that data retention errors do not occur. A mode register in the DRAM device may be programmed to select the size of the second set of memory cells.

公开(公告)号：US20160026533A1

公开(公告)日：2016-01-28

申请号：US14805072

申请日：2015-07-21

申请人： Micron Technology, Inc.

发明人： TORU ISHIKAWA

IPC分类号： G06F11/14

CPC分类号： G06F11/1441 ,  G06F2201/85 ,  G11C11/406 ,  G11C2029/0411 ,  G11C2211/4061 ,  G11C2211/4062

摘要： A device includes a plurality of memory cells, an error detection circuit configured to detect at least one memory cell storing error data and a refresh control circuit including a register configured to store an error address corresponding to the at least one memory cell storing error data. The refresh control circuit is configured to control a refresh cycle of the error address.

摘要翻译： 一种设备包括多个存储器单元，错误检测电路被配置为检测存储错误数据的至少一个存储单元和刷新控制电路，该刷新控制电路包括配置为存储与存储错误数据的至少一个存储单元相对应的错误地址的寄存器。 刷新控制电路被配置为控制错误地址的刷新周期。