公开(公告)号：US12125549B2

公开(公告)日：2024-10-22

申请号：US18362978

申请日：2023-08-01

申请人： MIMIRIP LLC

发明人： In Jong Jang

IPC分类号： G11C29/42 ,  G11C7/10 ,  G11C29/36 ,  G11C29/44

CPC分类号： G11C29/42 ,  G11C7/1057 ,  G11C7/1084 ,  G11C29/36 ,  G11C29/44

摘要： A data processing system includes a controller configured to receive a first encoded data item and a write request from a host, the first encoded data item being encoded based on a hamming code. The controller is further configured to store the first encoded data item in a write buffer, decode the first encoded data item stored in the write buffer based on the hamming code to detect and correct a first error in the first encoded data item to obtain a first error-corrected data item, encode the first error-corrected data item based on an error correction code to generate a second encoded data item, and transmit the second encoded data item to program the second encoded data item in a non-volatile memory device.

公开(公告)号：US20240331791A1

公开(公告)日：2024-10-03

申请号：US18193645

申请日：2023-03-31

申请人： NANYA TECHNOLOGY CORPORATION

发明人： Yi-Hsuan Chu

IPC分类号： G11C29/36 ,  G11C29/12 ,  G11C29/46

CPC分类号： G11C29/36 ,  G11C29/12015 ,  G11C29/46

摘要： A test method is for testing a decision feedback equalization (DFE) of a memory device is provided. The memory device includes a memory bank. The test method includes: providing a first test data pattern having a first data transition frequency and a second test data pattern having a second data transition frequency different from the first data transition frequency; writing the first test data pattern into a first memory section of the memory bank with a first DFE; writing the second test data pattern into a second memory section of the memory bank with the first DFE; reading a first reading data pattern stored in the first memory section and a second reading data pattern stored in the second memory section; and generating a test result signal according to the first reading data pattern and the second reading data pattern.

公开(公告)号：US20240321377A1

公开(公告)日：2024-09-26

申请号：US18737631

申请日：2024-06-07

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Ted Wong ,  Saman Adham ,  Marat Gershoig

IPC分类号： G11C29/38 ,  G11C29/36

CPC分类号： G11C29/38 ,  G11C29/36

摘要： Performing a built-in self-test (BIST) on a memory macro includes generating a plurality of input vectors. One input vector is transmitted to the memory macro in each of a plurality of cycles. Each of the plurality of input vectors is associated with a bit width. Generating the input vector includes generating a partial input vector of half the bit width and transmitting the partial input vector to each of a first half of the memory macro and a second half of the memory macro. The method also includes receiving, in each of the plurality of cycles, an output data from the memory macro, such that the output data is generated by the memory macro in response to processing the partial input vector, comparing the output data with a signature value, and determining whether the memory macro is normal or faulty based upon the comparison.

公开(公告)号：US20240290415A1

公开(公告)日：2024-08-29

申请号：US18341607

申请日：2023-06-26

申请人： SK hynix Inc.

发明人： Byeong Cheol LEE

IPC分类号： G11C29/46 ,  G11C29/36

CPC分类号： G11C29/46 ,  G11C29/36 ,  G11C2029/1202

摘要： A semiconductor device includes a test control circuit configured to enter a test mode and configured to generate a test word line precharge signal, based on a test mode entry signal, an active pulse, a precharge pulse, a reset signal, and a test code; a mat including a plurality of word line drivers; and a word line control circuit configured to generate a word line driving signal, a plurality of voltage driving signals, and a plurality of voltage discharge signals for controlling operations of the plurality of word line drivers, based on the test word line precharge signal, a mat enable signal, and a plurality of internal addresses. The word line driving signal is a signal that is enabled after a start of an active operation and that is disabled after a set period from timing for a precharge operation.

公开(公告)号：US12051476B2

公开(公告)日：2024-07-30

申请号：US17662862

申请日：2022-05-11

申请人： NXP USA, Inc.

发明人： Timothy Strauss ,  Jon Scott Choy ,  Michael A. Sadd

IPC分类号： G11C29/46 ,  G11C29/12 ,  G11C29/20 ,  G11C29/36

CPC分类号： G11C29/46 ,  G11C29/1201 ,  G11C29/20 ,  G11C29/36 ,  G11C2029/3602

摘要： Memory built-in self-test (MBIST) circuitry for a disruptive memory includes an address sequencer configured to select an address with the disruptive memory as a test location, and control circuitry configured to direct a test sequence including a plurality of test operations on the test location. The control circuitry includes a first fault counter and a second fault counter, in which the control circuitry is configured to, after each test operation of the test sequence, determine whether to selectively update a first fault counter and whether to selectively update a second fault counter. The address sequencer, after completion of the test sequence, selects a next address within the disruptive memory as a next test location.

公开(公告)号：US12020760B2

公开(公告)日：2024-06-25

申请号：US18078714

申请日：2022-12-09

申请人： STMicroelectronics International N.V.

发明人： Venkata Narayanan Srinivasan ,  Balwinder Singh Soni ,  Avneep Kumar Goyal

IPC分类号： G11C29/00 ,  G11C7/10 ,  G11C7/22 ,  G11C29/14 ,  G11C29/36 ,  G11C29/38 ,  G11C29/12 ,  H03K19/20

CPC分类号： G11C29/38 ,  G11C7/1084 ,  G11C7/22 ,  G11C29/14 ,  G11C29/36 ,  G11C2029/1206 ,  G11C2029/3602 ,  H03K19/20

摘要： Disclosed herein is a method of operating a system in a test mode. When the test mode is an ATPG test mode, the method includes beginning stuck-at testing by setting a scan control signal to a logic one, setting a transition mode signal to a logic 0, and initializing FIFO buffer for ATPG test mode. The FIFO buffer is initialized for ATPG test mode by setting a scan reset signal to a logic 0 to place a write data register and a read data register associated with the FIFO buffer into a reset state, enabling latches of the FIFO buffer using an external enable signal, removing the external enable signal to cause the latches to latch, and setting the scan reset signal to a logic 1 to release the write data register and the read data register from the reset state, while not clocking the write data register.

公开(公告)号：US20240153573A1

公开(公告)日：2024-05-09

申请号：US18411822

申请日：2024-01-12

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Jaspal Singh Shah ,  Atul Katoch

IPC分类号： G11C29/12 ,  G11C29/36 ,  G11C29/46

CPC分类号： G11C29/1201 ,  G11C29/12015 ,  G11C29/36 ,  G11C29/46 ,  G11C2029/3602

摘要： In some aspects of the present disclosure, a memory device is disclosed. In some aspects, the memory device includes a plurality of memory cells arranged in an array, an input/output (I/O) interface connected to the plurality of memory cells to output data signal from each memory cell, and a control circuit. In some embodiments, the control circuit includes a first clock generator to generate a first clock signal and a second clock signal according to an input clock signal and a chip enable (CE) signal and provide the first clock signal to the plurality of memory cells. In some embodiments, the control circuit includes a second clock generator to generate a third clock signal according to the input clock signal and a DFT (design for testability) enable signal. In some embodiments, the control circuit generates an output clock signal according to the second clock signal or the third clock signal.

公开(公告)号：US11961576B2

公开(公告)日：2024-04-16

申请号：US17604805

申请日：2019-08-27

申请人： Siemens Industry Software Inc

发明人： Benoit Nadeau-Dostie ,  Luc Romain

IPC分类号： G11C29/00 ,  G11C29/36 ,  G11C29/40 ,  G11C29/44

CPC分类号： G11C29/4401 ,  G11C29/36 ,  G11C29/40 ,  G11C2029/3602

摘要： Systems and methods for repairing a memory. A method includes performing a repair analysis of the embedded memories to produce repair information. The method includes storing the repair information in the registers, where the registers are organized into groups having chains of identical length. The method includes performing collision detection between the repair information in each of the groups. The method includes merging the repair information in each of the groups. The method includes repairing the embedded memories using the merged repair information.

公开(公告)号：US20240120016A1

公开(公告)日：2024-04-11

申请号：US18392740

申请日：2023-12-21

申请人： Texas Instruments Incorporated

发明人： Devanathan Varadarajan ,  Lei Wu

IPC分类号： G11C29/16 ,  G01R31/3185 ,  G11C29/02 ,  G11C29/10 ,  G11C29/12 ,  G11C29/14 ,  G11C29/26 ,  G11C29/32 ,  G11C29/36

CPC分类号： G11C29/16 ,  G01R31/318594 ,  G01R31/318597 ,  G11C29/022 ,  G11C29/023 ,  G11C29/10 ,  G11C29/1201 ,  G11C29/12015 ,  G11C29/14 ,  G11C29/26 ,  G11C29/32 ,  G11C29/36

摘要： Methods to test functional memory interface logic of a core under test utilize a built-in-self-test (BIST) controller to generate test sequences, and a clock-gating circuit to selectively supply the test sequences to a memory input or memory output on the core under test. After an initial data initialization of the core under test at BIST mode, an at-speed functional mode is utilized to capture a desired memory output.

公开(公告)号：US11948654B1

公开(公告)日：2024-04-02

申请号：US17662178

申请日：2022-05-05

申请人： Meta Platforms Technologies, LLC

发明人： Shrirang Madhav Yardi ,  Dinesh Patil ,  Neeraj Upasani

IPC分类号： G11C29/44 ,  G11C29/12 ,  G11C29/36 ,  G11C29/46

CPC分类号： G11C29/4401 ,  G11C29/12005 ,  G11C29/36 ,  G11C29/46

摘要： A system on a chip includes a first subsystem comprising a first memory; a second subsystem comprising a second memory; and an always-on subsystem. The always-on subsystem can comprise processing circuitry configured to: in response to a first activation event, signal the first subsystem to initiate repair operations on the first memory, and in response to a second activation event occurring after the first event, signal the second subsystem to initiate repair operations on the second memory.