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公开(公告)号：US20230229338A1
公开(公告)日：2023-07-20
申请号：US17900551
申请日：2022-08-31
IPC分类号： G06F3/06
CPC分类号： G06F3/0653 , G06F3/0604 , G06F3/0679
摘要： An example device includes: converter circuitry having an output configured to couple to a first memory circuit from a plurality of memory circuits, the converter circuitry configured to: receive a first instruction formatted with a uniform protocol; and convert the first instruction from the uniform protocol to a protocol specific to the first memory circuit; logic circuitry having an input configured to couple to the first memory circuit, the logic circuitry configured to: receive a first result of the first instruction from the first memory circuit; and responsive to a second instruction, combine the first result with other results from ones of the plurality of memory circuits into an output.
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公开(公告)号：US10600495B2
公开(公告)日：2020-03-24
申请号：US15891789
申请日：2018-02-08
摘要： In described examples of circuitry and methods for testing multiple memories, a controller generates a sequence of commands to be applied to one or more of the memories, where each given command includes expected data, and a command address. Local adapters are individually coupled with the controller and with an associated memory. Each local adapter translates the command to a memory type of the associated memory, maps the command address to a local address of the associated memory, and provides test results to the controller according to read data from the local address of the associated memory and the expected data of the command.
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3.发明申请公开(公告)号：US20190156908A1
公开(公告)日：2019-05-23
申请号：US16192796
申请日：2018-11-15
发明人： Devanathan Varadarajan , Lei Wu
IPC分类号： G11C29/16 , G11C29/10 , G11C29/12 , G11C29/32 , G01R31/3185
摘要： A device to test functional memory interface logic of a core under test is described herein. The device includes and utilizes a built in self test controller to generate test sequences, and a clock-gating circuit to selectively supply the test sequences to a memory input or memory output on the core under test. After an initial data initialization of the core under test at built in self test mode, an at-speed functional mode is utilized to capture a desired memory output.
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公开(公告)号：US20230409435A1
公开(公告)日：2023-12-21
申请号：US18239880
申请日：2023-08-30
CPC分类号： G06F11/1448 , H03M7/30 , G06F2201/82
摘要： One example includes an integrated circuit (IC). The IC includes non-volatile memory and logic. The logic is configured to receive repair code associated with a memory instance and assign a compression parameter to the repair code based on a configuration of the memory instance. The logic is also configured to compress the repair code based on the compression parameter to produce compressed repair code and to provide compressed repair data that includes the compressed repair code and compression control data that identifies the compression parameter. A non-volatile memory controller is coupled between the non-volatile memory and the logic. The non-volatile memory controller is configured to transfer the compressed repair data to and/or from the non-volatile memory.
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公开(公告)号：US11748202B2
公开(公告)日：2023-09-05
申请号：US17901337
申请日：2022-09-01
CPC分类号： G06F11/1448 , H03M7/30 , G06F2201/82
摘要： One example includes an integrated circuit (IC). The IC includes non-volatile memory and logic. The logic is configured to receive repair code associated with a memory instance and assign a compression parameter to the repair code based on a configuration of the memory instance. The logic is also configured to compress the repair code based on the compression parameter to produce compressed repair code and to provide compressed repair data that includes the compressed repair code and compression control data that identifies the compression parameter. A non-volatile memory controller is coupled between the non-volatile memory and the logic. The non-volatile memory controller is configured to transfer the compressed repair data to and/or from the non-volatile memory.
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公开(公告)号：US11568951B2
公开(公告)日：2023-01-31
申请号：US16817096
申请日：2020-03-12
IPC分类号： G11C29/00 , G11C29/38 , G11C29/50 , G11C11/419 , G11C11/418 , G11C11/412
摘要： Systems and methods of screening memory cells by modulating bitline and/or wordline voltage. In a read operation, the wordline may be overdriven or underdriven as compared to a nominal operating voltage on the wordline. In a write operation, the one or both of the bitline and wordline may be overdriven or underdriven as compared to a nominal operating voltage of each. A built-in self test (BIST) system for screening a memory array has bitline and wordline margin controls to modulate bitline and wordline voltage, respectively, in the memory array.
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公开(公告)号：US11436090B2
公开(公告)日：2022-09-06
申请号：US17125244
申请日：2020-12-17
摘要： One example includes an integrated circuit (IC). The IC includes non-volatile memory and logic. The logic is configured to receive repair code associated with a memory instance and assign a compression parameter to the repair code based on a configuration of the memory instance. The logic is also configured to compress the repair code based on the compression parameter to produce compressed repair code and to provide compressed repair data that includes the compressed repair code and compression control data that identifies the compression parameter. A non-volatile memory controller is coupled between the non-volatile memory and the logic. The non-volatile memory controller is configured to transfer the compressed repair data to and/or from the non-volatile memory.
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公开(公告)号：US09053799B2
公开(公告)日：2015-06-09
申请号：US14038306
申请日：2013-09-26
CPC分类号： G11C29/4401 , G11C17/16 , G11C17/18 , G11C29/38 , G11C29/785 , G11C29/789 , G11C2029/4402
摘要： A memory repair system in an integrated circuit (IC) that optimizes the fuseROM used for memory repair. The IC includes a plurality of memory wrappers. Each memory wrapper includes a memory block with a fuse register and a bypass register. The bypass register has a bypass data that indicates a defective memory wrapper of the plurality of memory wrappers. A fuseROM controller is coupled to the plurality of memory wrappers. A memory bypass chain links the bypass registers in the plurality of memory wrappers with the fuseROM controller. The fuseROM controller loads the bypass data in the memory bypass chain. A memory data chain links the fuse registers in the plurality of memory wrappers with the fuseROM controller. The memory data chain is re-configured to link the fuse registers in a set of defective memory wrappers of the plurality of memory wrappers responsive to the bypass data loaded in the memory bypass chain.
摘要翻译： 集成电路（IC）中的存储器修复系统，其优化用于存储器修复的熔丝ROM。 IC包括多个存储器包装器。 每个存储器包装器包括具有熔丝寄存器和旁路寄存器的存储器块。 旁路寄存器具有指示多个存储器包装器的有缺陷的存储器包装器的旁路数据。 熔丝ROM控制器耦合到多个存储器包装器。 存储器旁路链将多个存储器封装器中的旁路寄存器与熔丝ROM控制器链接。 fuseROM控制器将旁路数据加载到内存旁路链中。 存储器数据链将多个存储器包装器中的熔丝寄存器与熔丝ROM控制器链接。 存储器数据链被重新配置为响应于加载在存储器旁路链中的旁路数据，将多个存储器包装器中的一组缺陷存储器包装器中的熔丝寄存器链接。
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公开(公告)号：US20240345160A1
公开(公告)日：2024-10-17
申请号：US18749823
申请日：2024-06-21
IPC分类号： G01R31/317 , G01R31/28 , G01R31/3177 , G01R31/3185
CPC分类号： G01R31/31703 , G01R31/3177 , G01R31/2851 , G01R31/31724 , G01R31/318536 , G01R31/318547 , G01R31/318566 , G01R31/318586
摘要： An example device includes built in test observation controller circuitry configured to: obtain a test; send first instructions to the processor to begin to execute the test by modifying values stored in a plurality of memory circuits; send second instructions to the processor to stop execution of the test at a first simulation time, wherein one or more memory values that are unobservable during a second simulation time of the test execution are observable during the first simulation time; and enhanced chip access trace scan circuitry configured to select a subset of the values from the plurality of memory circuits while the test is stopped; and signature circuitry configured to: determine a logic signature based on the subset of the values; and provide the logic signature for comparison to an expected signature, wherein a difference between the logic signature and the expected signature corresponds to a fault in the processor.
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公开(公告)号：US20240170083A1
公开(公告)日：2024-05-23
申请号：US18057801
申请日：2022-11-22
CPC分类号： G11C29/1201 , G11C29/18 , G11C29/46
摘要： An electronic circuit includes: a memory including a data input, an address input, a command input, and a data output; a register having a data input coupled to the data output of the memory; a comparator circuit having a first data input coupled to the data output of the memory, and a second data input coupled to a data output of the register; an inverter circuit having a data input coupled to the data output of the register, and a data output coupled to the data input of the memory; and a controller having a command output coupled to the command input of the memory, an address output coupled to the address input of the memory, and a fault input coupled to a data output of the comparator circuit, where the controller is configured to determine whether the memory has a fault based on the fault input of the controller.
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