公开(公告)号：US12094528B2

公开(公告)日：2024-09-17

申请号：US17833852

申请日：2022-06-06

申请人： QUALCOMM Incorporated

发明人： Dhvani Sheth ,  Hochul Lee ,  Anil Chowdary Kota ,  Chulmin Jung

IPC分类号： G11C29/14 ,  G11C11/418 ,  G11C11/419

CPC分类号： G11C11/419 ,  G11C11/418

摘要： A memory is provided with a plurality of column groups and two redundant column groups. If there are two defective columns in the plurality of column groups, the plurality of column groups may be divided into a no-shift region, a one-shift region, and a two-shift region. The memory includes a plurality of input/output circuits corresponding to the plurality of column groups. Each input/output circuit may provide a data input signal during a write operation and receive a data output signal during a read operation. Each input/output circuit also includes a switch matrix. In the no-shift region, the switch matrix couples the input/output circuit to a core in the corresponding column group. In the one-shift region, the switch matrix couples the input/output circuit to a core in a subsequent column group. In the two-shift region, the switch matrix couples the input/output circuit to a core in a next-to-subsequent column group.

公开(公告)号：US12073899B2

公开(公告)日：2024-08-27

申请号：US17536462

申请日：2021-11-29

申请人： Micron Technology, Inc.

发明人： Sivagnanam Parthasarathy ,  James Fitzpatrick ,  Patrick Robert Khayat ,  AbdelHakim S. Alhussien

IPC分类号： G11C29/12 ,  G06F18/214 ,  G06N20/00 ,  G11C7/02 ,  G11C29/14 ,  G11C29/44

CPC分类号： G11C29/12005 ,  G06F18/214 ,  G06N20/00 ,  G11C7/02 ,  G11C29/14 ,  G11C29/44

摘要： A memory sub-system to track charge loss in memory cells and shifts of voltages optimized to read the memory cells. For example, a memory device can measure signal and noise characteristics of a group of memory cells to calculate an optimized read voltage of the group of memory cells. The memory sub-system having the memory device can determine an amount of charge loss in the group of memory cells, using at least the signal and noise characteristics, the optimized read voltage, and/or the bit error rate of data read using the optimized read voltage. The memory sub-system tracks changes in optimized read voltages of memory cells in the memory device based on the amount of charge loss.

公开(公告)号：US12072380B2

公开(公告)日：2024-08-27

申请号：US17883175

申请日：2022-08-08

申请人： Lodestar Licensing Group LLC

发明人： Antonino Mondello ,  Alberto Troia

IPC分类号： G01R31/3177 ,  G06F3/06 ,  G06F13/16 ,  G11C29/14 ,  G11C29/16 ,  G11C29/32

CPC分类号： G01R31/3177 ,  G06F3/0604 ,  G06F3/0655 ,  G06F3/0679 ,  G06F13/1668 ,  G11C29/14 ,  G11C29/16 ,  G11C29/32 ,  G11C2029/3202

摘要： The present disclosure relates to an apparatus comprising a host device and a memory component coupled to the host device. The memory component can comprise an array of memory cells, and an interface comprising a boundary scan architecture, wherein the boundary scan architecture includes an instruction register configured to store data indicative of a presence of a test data input (TDI) signal.

公开(公告)号：US12046315B2

公开(公告)日：2024-07-23

申请号：US17756963

申请日：2020-05-28

申请人： Siemens Industry Software Inc.

发明人： Jongsin Yun ,  Benoit Nadeau-Dostie ,  Martin Keim

IPC分类号： G11C29/14 ,  G11C29/12 ,  G11C29/46

CPC分类号： G11C29/14 ,  G11C29/1201 ,  G11C29/46

摘要： This application discloses a memory built-in self-test system to prompt a memory device to sense values of stored data using a reference trim during memory read operations. The memory built-in self-test system can automatically set the reference trim for the memory device. The memory built-in self-test system includes a memory built-in self-test controller to prompt the memory device to perform the memory read operations with different test values for the reference trim. The memory built-in self-test system also includes a trim feedback circuit to determine when the memory device fails to correctly sense the values of the stored data using the test values for the reference trim, and set the reference trim for the memory device based, at least in part, on the failures of the memory device to correctly sense the stored data.

公开(公告)号：US20240242773A1

公开(公告)日：2024-07-18

申请号：US18320667

申请日：2023-05-19

申请人： SK hynix Inc.

发明人： Gi Moon HONG ,  Dae Han KWON

IPC分类号： G11C29/12 ,  G11C7/10 ,  G11C7/22 ,  G11C29/14 ,  G11C29/18

CPC分类号： G11C29/12015 ,  G11C7/1066 ,  G11C7/222 ,  G11C29/14 ,  G11C29/18 ,  G11C2029/1802

摘要： A test circuit may include: a plurality of replication receivers configured to generate a plurality of oscillation signal pairs in response to a plurality of oscillation enable signals; and an oscillation control circuit configured to generate the plurality of oscillation enable signals in response to a test enable signal, and to generate a detection signal in response to any one of the plurality of oscillation signal pairs.

公开(公告)号：US20240212777A1

公开(公告)日：2024-06-27

申请号：US18146558

申请日：2022-12-27

申请人： Advanced Micro Devices, Inc.

发明人： Robin Conradine Knauerhase

IPC分类号： G11C29/14

CPC分类号： G11C29/14 ,  G11C2029/1208

摘要： Memory verification using processing-in-memory is described. In accordance with the described techniques, memory testing logic is loaded into a processing-in-memory component. The processing-in-memory component executes the memory testing logic to test a memory. An indication is output of a detected fault in the memory based on testing the memory.

公开(公告)号：US20240185942A1

公开(公告)日：2024-06-06

申请号：US18482300

申请日：2023-10-06

申请人： Samsung Electronics Co., Ltd.

发明人： Myungkyu Lee ,  Seongmuk Kang ,  Sunghye Cho ,  Daehyun Kim ,  Kyomin Sohn ,  Kijun Lee

IPC分类号： G11C29/42 ,  G11C29/14

CPC分类号： G11C29/42 ,  G11C29/14

摘要： A memory device includes a memory cell array and an error correction code (ECC) circuit. The ECC circuit, which is configured to correct an error in a data code read out from the memory cell array, includes: (i) a syndrome calculating unit configured to operate a plurality of syndromes based on the data code and an H-matrix, (ii) an error location detecting unit configured to generate an error vector based on the plurality of syndromes, and (iii) an error correcting unit configured to correct an error within the data code based on the error vector, and output corrected data.

公开(公告)号：US20240185940A1

公开(公告)日：2024-06-06

申请号：US18358567

申请日：2023-07-25

申请人： Western Digital Technologies, Inc.

发明人： Shabtay Yudkovich ,  David Avraham ,  Mahim Raj Gupta

IPC分类号： G11C29/14 ,  G11C29/12 ,  G11C29/42

CPC分类号： G11C29/14 ,  G11C29/1201 ,  G11C29/42

摘要： Technology is disclosed herein for memory health monitoring and mitigation based on decoding statistics. Decoding a frame results in a decoding metric (syndrome weight, fail bit count) for that frame. The system tracks a statistic for different sets of frames. The statistic for a set is based on the decoding metrics for that set. The frames may be assigned to sets based on read reference voltages used to read frames or the physical location of the memory cells that store the frames. Memory health mitigation may be performed based on the decoding statistics. One example mitigation is to modify the read reference voltages for the set. Another example mitigation is to trigger reading at soft bit reference levels for a block. Another example mitigation is to trigger direct look ahead reading for a block. Still another example mitigation is to add a block to list of candidates for data refresh.

公开(公告)号：US11990195B2

公开(公告)日：2024-05-21

申请号：US17935057

申请日：2022-09-23

申请人： Lodestar Licensing Group LLC

发明人： Boon Hor Lam ,  Shawn M. Hilde ,  Karl L. Major ,  Garrett Harwell

IPC分类号： G11C29/12 ,  G11C7/10 ,  G11C11/406 ,  G11C29/14 ,  G11C29/44

CPC分类号： G11C29/12015 ,  G11C7/1048 ,  G11C11/40615 ,  G11C29/14 ,  G11C29/44

摘要： Memory devices, systems including memory devices, and methods of operating memory devices are described, in which memory device are configured to add variable delays to a command. The variable delays may be provided by a host device (e.g., a test equipment) using a test mode of the memory devices. Alternatively, the variable delays may be stored in nonvolatile memory (NVM) components of the memory devices. Further, mode registers of the memory devices may be set to indicate that the command is associated with the variable delays stored in the NVM components. Further, the memory devices may include delay components configured to add the variable delays to the command. Such variable delays facilitate staggered execution of the command across multiple memory devices so as to avoid (or mitigate) issues related to an instantaneous, large amount of current drawn from a power supply connected to the memory devices.

公开(公告)号：US20240079076A1

公开(公告)日：2024-03-07

申请号：US18104907

申请日：2023-02-02

申请人： SK hynix Inc.

发明人： Hong Ki MOON

IPC分类号： G11C29/42 ,  G11C29/12 ,  G11C29/14

CPC分类号： G11C29/42 ,  G11C29/1201 ,  G11C29/14 ,  G11C2029/4402

摘要： An embodiment includes: an error information processing circuit configured to generate error information according to syndrome information; and a data correction circuit configured to correct an error in data according to the syndrome information. In a test mode, only the error information processing circuit between the error information processing circuit and the data correction circuit is configured to be activated.