公开(公告)号：US20240370206A1

公开(公告)日：2024-11-07

申请号：US18773373

申请日：2024-07-15

Applicant: Micron Technology, Inc.

Inventor： Kishore Kumar Muchherla ,  Violante Moschiano ,  Akira Goda ,  Jeffrey S. McNeil ,  Jung Sheng Hoei ,  Sivagnanam Parthasarathy ,  James Fitzpatrick ,  Patrick R. Khayat

IPC: G06F3/06

Abstract: Control logic in a memory device receives a request to read data from a memory array of a memory device, the request comprising an indication of a segment of the memory array where the data is stored, and determines whether a write temperature associated with the data is stored in a flag byte corresponding to the segment of the memory array. Responsive to determining that the write temperature associated with the data is stored in the flag byte, the control logic determines a cross-temperature for the data based on the write temperature and a read temperature at a time when the request to read the data is received, determines a program/erase cycle count associated with the segment of the memory array, and determines, based on the cross-temperature and the program/erase cycle count, whether to perform a corrective action to calibrate a read voltage level to be applied to the memory array to read the data from the segment.

公开(公告)号：US20240296896A1

公开(公告)日：2024-09-05

申请号：US18657672

申请日：2024-05-07

Applicant: Micron Technology, Inc.

Inventor： Patrick Robert Khayat ,  James Fitzpatrick ,  AbdelHakim S. Alhussien ,  Sivagnanam Parthasarathy

IPC: G11C16/34 ,  G06F18/214 ,  G06N20/00 ,  G11C7/02 ,  G11C16/10 ,  G11C16/26 ,  G11C16/30

CPC classification number: G11C16/3431 ,  G06F18/214 ,  G06N20/00 ,  G11C7/02 ,  G11C16/10 ,  G11C16/26 ,  G11C16/30

Abstract: A memory device to perform a read disturb mitigation operation. For example, the memory device can measure signal and noise characteristics of a group of memory cells to determine an optimized read voltage of the group of memory cells and determine a margin of read disturb accumulated in the group of memory cells. Subsequently, the memory device can identify the group of memory cells for the read disturb mitigation operation based on the margin of read disturb and a predetermined threshold.

公开(公告)号：US12067290B2

公开(公告)日：2024-08-20

申请号：US17591406

申请日：2022-02-02

Applicant: Micron Technology, Inc.

Inventor： Kishore Kumar Muchherla ,  Violante Moschiano ,  Akira Goda ,  Jeffrey S. McNeil ,  Jung Sheng Hoei ,  Sivagnanam Parthasarathy ,  James Fitzpatrick ,  Patrick R. Khayat

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0679

Abstract: Control logic in a memory device receives a request to read data from a memory array of a memory device, the request comprising an indication of a segment of the memory array where the data is stored, and determines whether a write temperature associated with the data is stored in a flag byte corresponding to the segment of the memory array. Responsive to determining that the write temperature associated with the data is stored in the flag byte, the control logic determines a cross-temperature for the data based on the write temperature and a read temperature at a time when the request to read the data is received, determines a program/erase cycle count associated with the segment of the memory array, and determines, based on the cross-temperature and the program/erase cycle count, whether to perform a corrective action to calibrate a read voltage level to be applied to the memory array to read the data from the segment.

公开(公告)号：US11990186B2

公开(公告)日：2024-05-21

申请号：US17724940

申请日：2022-04-20

Applicant: Micron Technology, Inc.

Inventor： Phong Sy Nguyen ,  James Fitzpatrick ,  Kishore Kumar Muchherla

IPC: G11C16/10 ,  G06F3/06 ,  G11C11/56 ,  G11C16/26 ,  G11C16/04

CPC classification number: G11C16/10 ,  G06F3/0604 ,  G06F3/0644 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0679 ,  G11C11/56 ,  G11C16/26 ,  G11C16/0483

Abstract: A memory system to store multiple bits of data in a memory cell. A memory device coarsely programs a threshold voltage of the memory cell to a first level representative of a combination of bit values according to a mapping between bit value combinations and threshold levels. The threshold levels are partitioned into groups, each containing a subset of the threshold levels and having associated read voltages separating threshold levels in the subset. A group identification of a first group, among the groups, containing the first level is determined for the memory cell. The memory device applies read voltages of different groups, interleaved in an increasing order in a sequence, to read the memory cell when a read voltage applied is associated with the first group. The data bits read back from the memory cell are used to finely program the threshold voltage of the memory cell.

公开(公告)号：US11984171B2

公开(公告)日：2024-05-14

申请号：US17841096

申请日：2022-06-15

Applicant: Micron Technology, Inc.

Inventor： James Fitzpatrick ,  Phong Sy Nguyen ,  Dung Viet Nguyen ,  Sivagnanam Parthasarathy

IPC: G11C7/00 ,  A63B24/00 ,  G11C16/26 ,  G11C16/34

CPC classification number: G11C16/3404 ,  A63B24/0075 ,  G11C16/26 ,  A63B2024/0068 ,  A63B2024/0093 ,  A63B2220/836 ,  A63B2230/06

Abstract: A memory system configured to dynamically adjust the amount of redundant information stored in memory cells of a wordline on an integrated circuit die based on a bit error rate. For example, in response to a determination that a bit error rate of the wordline is above a threshold, the memory system can store first data items as independent first codewords of an error correction code technique into a first portion of the memory cells of the wordline, generate second data items as redundant information from the first codewords, and store the second data items in a second portion of the memory cells of the wordline. If the bit error rate is below the threshold, third data items can be stored as independent second codewords of the same length as the first codewords in the memory cells of the wordline.

公开(公告)号：US11934266B2

公开(公告)日：2024-03-19

申请号：US17859468

申请日：2022-07-07

Applicant: Micron Technology, Inc.

Inventor： Vamsi Pavan Rayaprolu ,  Mustafa N. Kaynak ,  Sivagnanam Parthasarathy ,  Patrick Khayat ,  Sampath Ratnam ,  Kishore Kumar Muchherla ,  Jiangang Wu ,  James Fitzpatrick

IPC: G11C29/00 ,  G06F11/07 ,  G06F11/10

CPC classification number: G06F11/1068 ,  G06F11/076 ,  G06F11/0772

Abstract: Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations comprising selecting a source set of memory cells of the memory device, wherein the source set of memory cells are configured to store a first number of bits per memory cell; performing a data integrity check on the source set of memory cells to obtain a data integrity metric value; determining whether the data integrity metric value satisfies a threshold criterion; and responsive to determining that the data integrity metric value fails to satisfy the threshold criterion, causing the memory device to copy data from the source set of memory cells to a destination set of memory cells of the memory device, wherein the destination set of memory cells are configured to store a second number of bits per memory cell.

公开(公告)号：US20240071510A1

公开(公告)日：2024-02-29

申请号：US17899409

申请日：2022-08-30

Applicant: Micron Technology, Inc.

Inventor： Kishore Kumar Muchherla ,  Huai-Yuan Tseng ,  Giovanni Maria Paolucci ,  Dave Scott Ebsen ,  James Fitzpatrick ,  Akira Goda ,  Jeffrey S. McNeil ,  Umberto Siciliani ,  Daniel J. Hubbard ,  Walter Di Francesco ,  Michele Incarnati

IPC: G11C16/10 ,  G11C16/08 ,  G11C16/34

CPC classification number: G11C16/102 ,  G11C16/08 ,  G11C16/3404

Abstract: Exemplary methods, apparatuses, and systems including a programming manager for controlling writing data bits to a memory device. The programming manager receives a first set of data bits for programming to memory. The programming manager writes a first subset of data bits to a first wordline during a first pass of programming. The programming manager writes a second subset of data bits of the first set of data bits to a buffer. The programming manager receives a second set of data bits for programming. The programming manager writes the second subset of data bits of the first set of data bits to the first wordline during a second pass of programming to increase a bit density of memory cells in the first wordline in response to receiving the second set of data bits.

公开(公告)号：US20240071435A1

公开(公告)日：2024-02-29

申请号：US18198623

申请日：2023-05-17

Applicant: Micron Technology, Inc.

Inventor： Phong Sy Nguyen ,  Patrick R. Khayat ,  Jeffrey S. McNeil ,  Dung Viet Nguyen ,  Kishore Kumar Muchherla ,  James Fitzpatrick

IPC: G11C7/10

CPC classification number: G11C7/1069 ,  G11C7/1057 ,  G11C7/106

Abstract: Systems and methods are disclosed including a memory device comprising a memory array and control logic, operatively coupled with the memory array. The control logic can perform operations comprising causing a read operation to be initiated with respect to a set of target cells of the memory array; obtaining, for a respective group of adjacent cells, respective cell state information; performing a set of strobe reads on the set of target cells; and generating, for a target cell of the set of target cells, semi-soft bit data based on the respective cell state information of the respective group of adjacent cells and on data obtained from a first strobe read and a second strobe read of the set of strobe reads performed on the target cell.

公开(公告)号：US20230359388A1

公开(公告)日：2023-11-09

申请号：US17735458

申请日：2022-05-03

Applicant: Micron Technology, Inc.

Inventor： Dung Viet Nguyen ,  Patrick R. Khayat ,  Zhengang Chen ,  James Fitzpatrick ,  Sivagnanam Parthasarathy ,  Eric N. Lee

IPC: G06F3/06

CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0679

Abstract: Described are systems and methods for memory read calibration based on memory device-originated metadata characterizing voltage distributions. An example memory device comprises: a memory array comprising a plurality of memory cells electrically coupled to a plurality of wordlines; and a controller coupled to the memory array, the controller to perform operations comprising: receiving one or more metadata values characterizing threshold voltage distributions of a subset of the plurality of memory cells connected to one or more bitlines, wherein the one or more metadata values reflect a conductive state of the one or more bitlines; determining a read voltage adjustment value based on the one or more metadata values; and applying the read voltage adjustment value for reading the subset of the plurality of memory cells.

公开(公告)号：US11726719B2

公开(公告)日：2023-08-15

申请号：US17939812

申请日：2022-09-07

Applicant: Micron Technology, Inc.

Inventor： Sivagnanam Parthasarathy ,  James Fitzpatrick ,  Patrick Robert Khayat ,  AbdelHakim S. Alhussien

IPC: G11C11/10 ,  G06F3/06 ,  G11C16/26 ,  G11C16/04 ,  G11C16/10

CPC classification number: G06F3/0659 ,  G06F3/0619 ,  G06F3/0679 ,  G11C16/26 ,  G11C16/0483 ,  G11C16/10

Abstract: A memory sub-system configured to: measure a plurality of sets of signal and noise characteristics of a group of memory cells in a memory device; determine a plurality of optimized read voltages of the group of memory cells from the plurality of sets of signal and noise characteristics respectively; generate features from the plurality of sets of signal and noise characteristics, including at least one compound feature generated from the plurality of sets of signal and noise characteristics; generate, using the features, a classification of a bit error rate of data retrievable from the group of memory cells; and control an operation to read the group of memory cells based on the classification.