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公开(公告)号：US20240347128A1
公开(公告)日：2024-10-17
申请号：US18753389
申请日：2024-06-25
Applicant: Micron Technology, Inc.
Inventor： Kishore Kumar Muchherla , Akira Goda , Dave Scott Ebsen , Lakshmi Kalpana Vakati , Jiangli Zhu , Peter Feeley , Sanjay Subbarao , Vivek Shivhare , Fangfang Zhu
CPC classification number: G11C29/52 , G11C29/022
Abstract: Methods, systems, and apparatuses include retrieving a defectivity footprint of a portion of memory, the portion of memory composed of multiple blocks. A deck programming order is determined, based on the defectivity footprint, for a current block of the multiple blocks. The current block is composed of multiple decks. The deck programming order is an order in which the multiple decks are programmed. The multiple decks programmed according to the determined deck programming order.
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公开(公告)号：US20240071510A1
公开(公告)日：2024-02-29
申请号：US17899409
申请日：2022-08-30
Applicant: Micron Technology, Inc.
Inventor： Kishore Kumar Muchherla , Huai-Yuan Tseng , Giovanni Maria Paolucci , Dave Scott Ebsen , James Fitzpatrick , Akira Goda , Jeffrey S. McNeil , Umberto Siciliani , Daniel J. Hubbard , Walter Di Francesco , Michele Incarnati
CPC classification number: G11C16/102 , G11C16/08 , G11C16/3404
Abstract: Exemplary methods, apparatuses, and systems including a programming manager for controlling writing data bits to a memory device. The programming manager receives a first set of data bits for programming to memory. The programming manager writes a first subset of data bits to a first wordline during a first pass of programming. The programming manager writes a second subset of data bits of the first set of data bits to a buffer. The programming manager receives a second set of data bits for programming. The programming manager writes the second subset of data bits of the first set of data bits to the first wordline during a second pass of programming to increase a bit density of memory cells in the first wordline in response to receiving the second set of data bits.
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公开(公告)号：US20240028259A1
公开(公告)日：2024-01-25
申请号：US17870139
申请日：2022-07-21
Applicant: Micron Technology, Inc.
Inventor： Kishore Kumar Muchherla , Peter Feeley , Jiangli Zhu , Fangfang Zhu , Akira Goda , Lakshmi Kalpana Vakati , Vivek Shivhare , Dave Scott Ebsen , Sanjay Subbarao
IPC: G06F3/06
CPC classification number: G06F3/0659 , G06F3/0604 , G06F3/0679
Abstract: Methods, systems, and apparatuses include receiving a write command including user data. The write command is directed to a portion of memory including a first block and a second block. A buffer is allocated for executing the write command to the first block. The buffer includes multiple buffer decks and the buffer holds the user data written to the first block. User data is programmed into the first block to a threshold percentage. The threshold percentage is less than one hundred percent of the first block. A buffer deck is invalidated in response to programming the first block to the threshold percentage. The buffer deck is reallocated to the second block for programming the user data into the second block. The buffer deck holds user data written to the second block.
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公开(公告)号：US12068034B2
公开(公告)日：2024-08-20
申请号：US17899409
申请日：2022-08-30
Applicant: Micron Technology, Inc.
Inventor： Kishore Kumar Muchherla , Huai-Yuan Tseng , Giovanni Maria Paolucci , Dave Scott Ebsen , James Fitzpatrick , Akira Goda , Jeffrey S. McNeil , Umberto Siciliani , Daniel J. Hubbard , Walter Di Francesco , Michele Incarnati
CPC classification number: G11C16/102 , G11C16/08 , G11C16/3404
Abstract: Exemplary methods, apparatuses, and systems including a programming manager for controlling writing data bits to a memory device. The programming manager receives a first set of data bits for programming to memory. The programming manager writes a first subset of data bits to a first wordline during a first pass of programming. The programming manager writes a second subset of data bits of the first set of data bits to a buffer. The programming manager receives a second set of data bits for programming. The programming manager writes the second subset of data bits of the first set of data bits to the first wordline during a second pass of programming to increase a bit density of memory cells in the first wordline in response to receiving the second set of data bits.
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公开(公告)号：US20240029815A1
公开(公告)日：2024-01-25
申请号：US17872567
申请日：2022-07-25
Applicant: Micron Technology, Inc.
Inventor： Kishore Kumar Muchherla , Akira Goda , Dave Scott Ebsen , Lakshmi Kalpana Vakati , Jiangli Zhu , Peter Feeley , Sanjay Subbarao , Vivek Shivhare , Fangfang Zhu
CPC classification number: G11C29/52 , G11C29/022
Abstract: Methods, systems, and apparatuses include retrieving a defectivity footprint of a portion of memory, the portion of memory composed of multiple blocks. A deck programming order is determined, based on the defectivity footprint, for a current block of the multiple blocks. The current block is composed of multiple decks. The deck programming order is an order in which the multiple decks are programmed. The multiple decks programmed according to the determined deck programming order.
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Patent Agency Ranking
公开(公告)号：US12131060B2
公开(公告)日：2024-10-29
申请号：US17872426
申请日：2022-07-25
Applicant: Micron Technology, Inc.
Inventor： Kishore Kumar Muchherla , Dung V. Nguyen , Dave Scott Ebsen , Tomoharu Tanaka , James Fitzpatrick , Huai-Yuan Tseng , Akira Goda , Eric N. Lee
IPC: G06F3/06
CPC classification number: G06F3/0655 , G06F3/0604 , G06F3/064 , G06F3/0679
Abstract: Exemplary methods, apparatuses, and systems include a quick charge loss (QCL) mitigation manager for controlling writing data bits to a memory device. The QCL mitigation manager receives a first set of data bits for programming to memory. The QCL mitigation manager writes a first subset of data bits of the first set of data bits to a first memory block of the memory during a first pass of programming. The QCL mitigation manager writes a second subset of data bits of the first set of data bits to the first memory block during a second pass of programming in response to determining that the threshold delay is satisfied.
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公开(公告)号：US20240302999A1
公开(公告)日：2024-09-12
申请号：US18651590
申请日：2024-04-30
Applicant: Micron Technology, Inc.
Inventor： Kishore Kumar Muchherla , Lakshmi Kalpana Vakati , Dave Scott Ebsen , Peter Feeley , Sanjay Subbarao , Vivek Shivhare , Jiangli Zhu , Fangfang Zhu , Akira Goda
IPC: G06F3/06
CPC classification number: G06F3/0659 , G06F3/0619 , G06F3/064 , G06F3/0656 , G06F3/0683
Abstract: Methods, systems, and apparatuses include receiving a write command including user data. The write command is directed to a portion of memory including a first and second block and a first and second user data portion are directed to the first and second block. Temporary parity data is generated using the first and second user data portions. The temporary parity data and the first and second user data portions are stored in a buffer. Portions of the first and second block are programmed with two programming passes. The first and second user data portions in the buffer are invalidated in response to a completion of the second programming pass of the portions of the first and second blocks. The temporary parity data is maintained in the buffer until a second programming pass of the first and second block.
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公开(公告)号：US12079517B2
公开(公告)日：2024-09-03
申请号：US17870139
申请日：2022-07-21
Applicant: Micron Technology, Inc.
Inventor： Kishore Kumar Muchherla , Peter Feeley , Jiangli Zhu , Fangfang Zhu , Akira Goda , Lakshmi Kalpana Vakati , Vivek Shivhare , Dave Scott Ebsen , Sanjay Subbarao
IPC: G06F3/06
CPC classification number: G06F3/0659 , G06F3/0604 , G06F3/0679
Abstract: Methods, systems, and apparatuses include receiving a write command including user data. The write command is directed to a portion of memory including a first block and a second block. A buffer is allocated for executing the write command to the first block. The buffer includes multiple buffer decks and the buffer holds the user data written to the first block. User data is programmed into the first block to a threshold percentage. The threshold percentage is less than one hundred percent of the first block. A buffer deck is invalidated in response to programming the first block to the threshold percentage. The buffer deck is reallocated to the second block for programming the user data into the second block. The buffer deck holds user data written to the second block.
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公开(公告)号：US12051479B2
公开(公告)日：2024-07-30
申请号：US17872567
申请日：2022-07-25
Applicant: Micron Technology, Inc.
Inventor： Kishore Kumar Muchherla , Akira Goda , Dave Scott Ebsen , Lakshmi Kalpana Vakati , Jiangli Zhu , Peter Feeley , Sanjay Subbarao , Vivek Shivhare , Fangfang Zhu
CPC classification number: G11C29/52 , G11C29/022
Abstract: Methods, systems, and apparatuses include retrieving a defectivity footprint of a portion of memory, the portion of memory composed of multiple blocks. A deck programming order is determined, based on the defectivity footprint, for a current block of the multiple blocks. The current block is composed of multiple decks. The deck programming order is an order in which the multiple decks are programmed. The multiple decks programmed according to the determined deck programming order.
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公开(公告)号：US20250013382A1
公开(公告)日：2025-01-09
申请号：US18895273
申请日：2024-09-24
Applicant: Micron Technology, Inc.
Inventor： Kishore Kumar Muchherla , Dung V. Nguyen , Dave Scott Ebsen , Tomoharu Tanaka , James Fitzpatrick , Huai-Yuan Tseng , Akira Goda , Eric N. Lee
IPC: G06F3/06
Abstract: Exemplary methods, apparatuses, and systems include a quick charge loss (QCL) mitigation manager for controlling writing data bits to a memory device. The QCL mitigation manager receives a first set of data bits for programming to memory. The QCL mitigation manager writes a first subset of data bits of the first set of data bits to a first memory block of the memory during a first pass of programming. The QCL mitigation manager writes a second subset of data bits of the first set of data bits to the first memory block during a second pass of programming in response to determining that the threshold delay is satisfied.
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