公开(公告)号：US20250021488A1

公开(公告)日：2025-01-16

申请号：US18899895

申请日：2024-09-27

Applicant: Micron Technology, Inc.

Inventor： Sanjay Subbarao

IPC: G06F12/1009 ,  G06F12/0875

Abstract: A request that specifies a logical address associated with a host-initiated operation directed at a first portion of a memory device is received. A logical to physical (L2P) table is accessed. The L2P table comprises a mapping between logical addresses and physical addresses in a second portion of the memory device. An entry in the L2P table that corresponds to the logical address is identified and is determined to point to an entry in a read cache table. Based on an entry number of the entry in the read cache table, a chunk address of a chunk from among multiple chunks of a read cache is calculated. A physical address that corresponds to the logical address specified by the request is identified by accessing the chunk of read cache. The host-initiated operation is performed at a physical location within the first portion of the memory device corresponding the physical address.

公开(公告)号：US20250013579A1

公开(公告)日：2025-01-09

申请号：US18893262

申请日：2024-09-23

Applicant: Micron Technology, Inc.

Inventor： Sanjay Subbarao

IPC: G06F12/1009 ,  G06F12/0815 ,  G11C11/56 ,  G11C14/00 ,  G11C16/04

Abstract: A processing device receives a request specifying a logical address associated with a host-initiated operation directed at a first portion of a memory device. The processing device accesses a second L2P table comprising a mapping between logical addresses and physical addresses in a second portion of the memory device. A physical location within the second portion of the memory device is identified based on the second L2P table. The physical location corresponds to a portion of a first L2P table that specifies a physical address within the first portion of the memory device that corresponds to the logical address. The physical address is identified based on the portion of the first L2P table and the host-initiated operation is performed at the physical address.

公开(公告)号：US12124380B2

公开(公告)日：2024-10-22

申请号：US18223843

申请日：2023-07-19

Applicant: Micron Technology, Inc.

Inventor： Sanjay Subbarao

IPC: G06F12/10 ,  G06F12/0815 ,  G06F12/1009 ,  G11C16/04 ,  G11C11/56 ,  G11C14/00

CPC classification number: G06F12/1009 ,  G06F12/0815 ,  G11C16/0483 ,  G06F2212/7201 ,  G11C11/56 ,  G11C14/0018

Abstract: A processing device receives a request specifying a logical address associated with a host-initiated operation directed at a first portion of a memory device. The processing device accesses a second L2P table comprising a mapping between logical addresses and physical addresses in a second portion of the memory device. A physical location within the second portion of the memory device is identified based on the second L2P table. The physical location corresponds to a portion of a first L2P table that specifies a physical address within the first portion of the memory device that corresponds to the logical address. The physical address is identified based on the portion of the first L2P table and the host-initiated operation is performed at the physical address.

公开(公告)号：US20240302999A1

公开(公告)日：2024-09-12

申请号：US18651590

申请日：2024-04-30

Applicant: Micron Technology, Inc.

Inventor： Kishore Kumar Muchherla ,  Lakshmi Kalpana Vakati ,  Dave Scott Ebsen ,  Peter Feeley ,  Sanjay Subbarao ,  Vivek Shivhare ,  Jiangli Zhu ,  Fangfang Zhu ,  Akira Goda

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0656 ,  G06F3/0683

Abstract: Methods, systems, and apparatuses include receiving a write command including user data. The write command is directed to a portion of memory including a first and second block and a first and second user data portion are directed to the first and second block. Temporary parity data is generated using the first and second user data portions. The temporary parity data and the first and second user data portions are stored in a buffer. Portions of the first and second block are programmed with two programming passes. The first and second user data portions in the buffer are invalidated in response to a completion of the second programming pass of the portions of the first and second blocks. The temporary parity data is maintained in the buffer until a second programming pass of the first and second block.

公开(公告)号：US12079517B2

公开(公告)日：2024-09-03

申请号：US17870139

申请日：2022-07-21

Applicant: Micron Technology, Inc.

Inventor： Kishore Kumar Muchherla ,  Peter Feeley ,  Jiangli Zhu ,  Fangfang Zhu ,  Akira Goda ,  Lakshmi Kalpana Vakati ,  Vivek Shivhare ,  Dave Scott Ebsen ,  Sanjay Subbarao

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0679

Abstract: Methods, systems, and apparatuses include receiving a write command including user data. The write command is directed to a portion of memory including a first block and a second block. A buffer is allocated for executing the write command to the first block. The buffer includes multiple buffer decks and the buffer holds the user data written to the first block. User data is programmed into the first block to a threshold percentage. The threshold percentage is less than one hundred percent of the first block. A buffer deck is invalidated in response to programming the first block to the threshold percentage. The buffer deck is reallocated to the second block for programming the user data into the second block. The buffer deck holds user data written to the second block.

公开(公告)号：US12051479B2

公开(公告)日：2024-07-30

申请号：US17872567

申请日：2022-07-25

Applicant: Micron Technology, Inc.

Inventor： Kishore Kumar Muchherla ,  Akira Goda ,  Dave Scott Ebsen ,  Lakshmi Kalpana Vakati ,  Jiangli Zhu ,  Peter Feeley ,  Sanjay Subbarao ,  Vivek Shivhare ,  Fangfang Zhu

IPC: G11C29/52 ,  G11C29/02

CPC classification number: G11C29/52 ,  G11C29/022

Abstract: Methods, systems, and apparatuses include retrieving a defectivity footprint of a portion of memory, the portion of memory composed of multiple blocks. A deck programming order is determined, based on the defectivity footprint, for a current block of the multiple blocks. The current block is composed of multiple decks. The deck programming order is an order in which the multiple decks are programmed. The multiple decks programmed according to the determined deck programming order.

公开(公告)号：US12050809B2

公开(公告)日：2024-07-30

申请号：US17675888

申请日：2022-02-18

Applicant: Micron Technology, Inc.

Inventor： Sanjay Subbarao ,  Steven S. Williams ,  Mark Ish ,  John Edward Maroney

IPC: G06F3/06 ,  G06F12/10

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0644 ,  G06F3/0673 ,  G06F12/10

Abstract: A memory sub-system having memory cells formed on a plurality of integrated circuit dies. After receiving a command from a host system to store data, the memory sub-system queues the command to allocate pages of memory cells in a plurality of dies in the plurality of integrated circuit dies based on a determination that each of the plurality of dies is available to perform a data programming operation for the command. Based on the page application, the memory sub-system generates a portion of a media layout to at least map logical addresses of the data identified in the command to the allocated pages and receives the data from the host system. The memory sub-system stores the data into the pages using a multi-pass programming technique, where an atomic multi-pass programming operation can be configured to use at least two pages in separate planes in one or more dies in the plurality of integrated circuit dies to program at least a portion of the data.

公开(公告)号：US12045168B2

公开(公告)日：2024-07-23

申请号：US17942725

申请日：2022-09-12

Applicant: Micron Technology, Inc.

Inventor： Sanjay Subbarao

IPC: G06F12/0844 ,  G11C11/417

CPC classification number: G06F12/0844 ,  G06F2212/1024 ,  G11C11/417

Abstract: A memory sub-system configured to schedule the transfer of data from a host system for write commands to reduce the amount and time of data being buffered in the memory sub-system. For example, after receiving a plurality of streams of write commands from a host system, the memory sub-system identifies a plurality of media units in the memory sub-system for concurrent execution of a plurality of write commands respectively. In response to the plurality of commands being identified for concurrent execution in the plurality of media units respectively, the memory sub-system initiates communication of the data of the write commands from the host system to a local buffer memory of the memory sub-system. The memory sub-system has capacity to buffer write commands in a queue, for possible out of order execution, but limited capacity for buffering only the data of a portion of the write commands that are about to be executed.

公开(公告)号：US11868287B2

公开(公告)日：2024-01-09

申请号：US17407411

申请日：2021-08-20

Applicant: Micron Technology, Inc.

Inventor： Johnny A Lam ,  Alex J. Wesenberg ,  Guanying Wu ,  Sanjay Subbarao ,  Chandra Guda

IPC: G06F13/00 ,  G06F13/16 ,  G06F9/50 ,  G06F13/37

CPC classification number: G06F13/1673 ,  G06F9/5016 ,  G06F13/161 ,  G06F13/37 ,  G06F2209/503 ,  G06F2209/5011

Abstract: The memory sub-systems of the present disclosure discloses a just-in-time (JIT) scheduling system and method. In one embodiment, a system receives a request to perform a memory operation using a hardware resource associated with a memory device. The system identifies a traffic class corresponding to the memory operation. The system determines a number of available quality of service (QoS) credits for the traffic class during a current scheduling time frame. The system determines a number of QoS credits associated with a type of the memory operation. Responsive to determining the number of QoS credits associated with the type of the memory operation is less than the number of available QoS credits, the system submits the memory operation to be processed at a memory device.

公开(公告)号：US20230367719A1

公开(公告)日：2023-11-16

申请号：US18225958

申请日：2023-07-25

Applicant: Micron Technology, Inc.

Inventor： Sanjay Subbarao

IPC: G06F12/1009 ,  G06F12/0875

CPC classification number: G06F12/1009 ,  G06F12/0875 ,  G06F2212/608

Abstract: A request that specifies a logical address associated with a host-initiated operation directed at a first portion of a memory device is received. A logical to physical (L2P) table is accessed. The L2P table comprises a mapping between logical addresses and physical addresses in a second portion of the memory device. An entry in the L2P table that corresponds to the logical address is identified and is determined to point to an entry in a read cache table. Based on an entry number of the entry in the read cache table, a chunk address of a chunk from among multiple chunks of a read cache is calculated. A physical address that corresponds to the logical address specified by the request is identified by accessing the chunk of read cache. The host-initiated operation is performed at a physical location within the first portion of the memory device corresponding the physical address.