公开(公告)号：US12135645B2

公开(公告)日：2024-11-05

申请号：US18203569

申请日：2023-05-30

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  John Eric Linstadt ,  Christopher Haywood

IPC: G06F12/0804 ,  G06F12/12 ,  G11C14/00

Abstract: A hybrid volatile/non-volatile memory module employs a relatively fast, durable, and expensive dynamic, random-access memory (DRAM) cache to store a subset of data from a larger amount of relatively slow and inexpensive nonvolatile memory (NVM). A module controller prioritizes accesses to the DRAM cache for improved speed performance and to minimize programming cycles to the NVM. Data is first written to the DRAM cache where it can be accessed (written to and read from) without the aid of the NVM. Data is only written to the NVM when that data is evicted from the DRAM cache to make room for additional data. Mapping tables relating NVM addresses to physical addresses are distributed throughout the DRAM cache using cache line bits that are not used for data.

公开(公告)号：US12086039B2

公开(公告)日：2024-09-10

申请号：US18096812

申请日：2023-01-13

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  J. James Tringali ,  Ely Tsern

IPC: G06F11/14 ,  G06F3/06 ,  G11C7/20 ,  G11C14/00

CPC classification number: G06F11/1471 ,  G06F3/0619 ,  G06F3/0634 ,  G06F3/0647 ,  G06F3/0685 ,  G11C7/20 ,  G11C14/0018 ,  G06F2201/805 ,  G06F2201/84

Abstract: The embodiments described herein describe technologies for non-volatile memory persistence in a multi-tiered memory system including two or more memory technologies for volatile memory and non-volatile memory.

公开(公告)号：US12057837B2

公开(公告)日：2024-08-06

申请号：US17485226

申请日：2021-09-24

Applicant: iCometrue Company Ltd.

Inventor： Jin-Yuan Lee ,  Mou-Shiung Lin

IPC: H03K19/1776 ,  G11C11/16 ,  G11C11/412 ,  G11C11/419 ,  G11C13/00 ,  G11C14/00 ,  H01L23/00 ,  H01L23/498 ,  H01L23/538 ,  H01L25/18 ,  H03K19/0948 ,  H03K19/173 ,  H03K19/17728 ,  H03K19/20 ,  H10B10/00 ,  H10B61/00 ,  H10B63/00 ,  H10N70/00 ,  H03K19/21

CPC classification number: H03K19/1776 ,  G11C11/1673 ,  G11C11/412 ,  G11C11/419 ,  G11C13/0007 ,  G11C13/0038 ,  G11C13/004 ,  G11C14/0081 ,  G11C14/009 ,  H01L23/49811 ,  H01L23/5386 ,  H01L24/13 ,  H01L24/16 ,  H01L25/18 ,  H03K19/0948 ,  H03K19/1737 ,  H03K19/17728 ,  H03K19/20 ,  H10B10/00 ,  H10B10/15 ,  H10B61/00 ,  H10B61/10 ,  H10B63/00 ,  H10B63/20 ,  H10B63/30 ,  H10B63/80 ,  H10N70/826 ,  H10N70/841 ,  H10N70/8833 ,  G11C2213/15 ,  H01L2224/13023 ,  H01L2224/13024 ,  H01L2224/13082 ,  H01L2224/13147 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/81191 ,  H01L2224/81447 ,  H01L2224/83104 ,  H01L2224/92225 ,  H01L2224/97 ,  H01L2924/1431 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1443 ,  H03K19/21 ,  H01L2224/97 ,  H01L2224/81 ,  H01L2224/83104 ,  H01L2924/00014 ,  H01L2224/81447 ,  H01L2924/00014

Abstract: A field-programmable-gate-array (FPGA) integrated-circuit (IC) chip configured to perform a logic function based on a look-up table (LUT), includes: multiple non-volatile memory cells therein configured to store multiple resulting values of the look-up table (LUT); and a programmable logic block therein having multiple static-random-access-memory (SRAM) cells configured to store the resulting values passed from the non-volatile memory cells, wherein the programmable logic block is configured to select, in accordance with one of the combinations of its inputs, one from the resulting values stored in the static-random-access-memory (SRAM) cells into its output.

公开(公告)号：US20240185917A1

公开(公告)日：2024-06-06

申请号：US18441881

申请日：2024-02-14

Applicant: Zeno Semiconductor, Inc.

Inventor： Yuniarto Widjaja

IPC: G11C14/00 ,  G11C11/402 ,  G11C11/404 ,  G11C11/4074 ,  G11C11/56 ,  G11C13/00 ,  G11C16/04 ,  H01L29/66 ,  H01L29/78 ,  H01L29/788 ,  H10B12/00 ,  H10B12/10 ,  H10B63/00 ,  H10B99/00 ,  H10N70/00 ,  H10N70/20

CPC classification number: G11C14/0045 ,  G11C11/4026 ,  G11C11/404 ,  G11C11/4074 ,  G11C11/56 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/003 ,  G11C13/0038 ,  G11C13/0097 ,  G11C14/0018 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7841 ,  H01L29/7881 ,  H10B12/10 ,  H10B12/20 ,  H10B63/00 ,  H10B99/00 ,  H10N70/231 ,  H10N70/883 ,  G11C16/0416 ,  G11C2211/4016 ,  G11C2213/76 ,  G11C2213/79 ,  H10N70/8828

Abstract: A semiconductor memory cell and arrays of memory cells are provided In at least one embodiment, a memory cell includes a substrate having a top surface, the substrate having a first conductivity type selected from a p-type conductivity type and an n-type conductivity type; a first region having a second conductivity type selected from the p-type and n-type conductivity types, the second conductivity type being different from the first conductivity type, the first region being formed in the substrate and exposed at the top surface; a second region having the second conductivity type, the second region being formed in the substrate, spaced apart from the first region and exposed at the top surface; a buried layer in the substrate below the first and second regions, spaced apart from the first and second regions and having the second conductivity type; a body region formed between the first and second regions and the buried layer, the body region having the first conductivity type; a gate positioned between the first and second regions and above the top surface; and a nonvolatile memory configured to store data upon transfer from the body region.

公开(公告)号：US11990196B2

公开(公告)日：2024-05-21

申请号：US18179434

申请日：2023-03-07

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Adolf Baumann ,  Mark Jung

IPC: G11C29/36 ,  G11C14/00 ,  G11C5/14

CPC classification number: G11C29/36 ,  G11C14/0063 ,  G11C5/148 ,  G11C2029/3602

Abstract: A digital system includes a non-volatile calculating register having a set of latches configured to perform a calculation. A set of non-volatile storage cells is coupled to the set of latches. Access detection logic is coupled to the calculating register and is operable to initiate a calculation of a next value by the calculating register each time the calculating register is accessed by an accessing module. The access detection logic is operable to cause the next value to be stored in the set of non-volatile storage cells at the completion of the calculation as an atomic transaction. After a power loss or other restore event, the contents of the calculating register may be restored from the non-volatile storage cells.

公开(公告)号：US11984164B2

公开(公告)日：2024-05-14

申请号：US18300706

申请日：2023-04-14

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Perng-Fei Yuh ,  Yih Wang ,  Ku-Feng Lin ,  Jui-Che Tsai ,  Hiroki Noguchi ,  Fu-An Wu

IPC: G11C14/00 ,  G11C11/16 ,  G11C11/419

CPC classification number: G11C14/0081 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/1675 ,  G11C11/419

Abstract: Disclosed herein is an integrated circuit including multiple magnetic tunneling junction (MTJ) cells coupled to a static random access memory (SRAM). In one aspect, the integrated circuit includes a SRAM having a first port and a second port, and a set of pass transistors coupled to the first port of the SRAM. In one aspect, the integrated circuit includes a set of MTJ cells, where each of the set of MTJ cells is coupled between a select line and a corresponding one of the set of pass transistors.

公开(公告)号：US20240127889A1

公开(公告)日：2024-04-18

申请号：US18538220

申请日：2023-12-13

Applicant: Zeno Semiconductor, Inc.

Inventor： Yuniarto Widjaja

IPC: G11C14/00 ,  G11C11/404 ,  G11C11/56 ,  G11C16/06 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78 ,  H01L29/788 ,  H10B12/00 ,  H10B41/30 ,  H10B41/35

CPC classification number: G11C14/0018 ,  G11C11/404 ,  G11C11/565 ,  G11C16/06 ,  H01L29/0649 ,  H01L29/42328 ,  H01L29/4916 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7841 ,  H01L29/788 ,  H01L29/7881 ,  H10B12/00 ,  H10B12/20 ,  H10B41/30 ,  H10B41/35 ,  G11C16/0416

Abstract: A semiconductor memory cell includes a floating body region configured to be charged to a level indicative of a state of the memory cell; a first region in electrical contact with said floating body region; a second region in electrical contact with said floating body region and spaced apart from said first region; and a gate positioned between said first and second regions. The cell may be a multi-level cell. Arrays of memory cells are disclosed for making a memory device. Methods of operating memory cells are also provided.

公开(公告)号：US20240104037A1

公开(公告)日：2024-03-28

申请号：US18216543

申请日：2023-06-29

Applicant: Rambus Inc.

Inventor： Scott C. Best

IPC: G06F13/362 ,  G06F13/40 ,  G11C11/408 ,  G11C11/409 ,  G11C11/4096 ,  G11C14/00 ,  G11C16/10 ,  G11C16/26 ,  H01L23/00 ,  H01L23/48 ,  H01L23/50 ,  H01L23/60 ,  H01L25/065 ,  H01L27/02

CPC classification number: G06F13/362 ,  G06F13/4068 ,  G11C11/408 ,  G11C11/409 ,  G11C11/4096 ,  G11C14/0018 ,  G11C16/10 ,  G11C16/26 ,  H01L23/481 ,  H01L23/50 ,  H01L23/60 ,  H01L24/09 ,  H01L25/0652 ,  H01L25/0657 ,  H01L27/0248 ,  H01L23/48 ,  H01L2224/0401 ,  H01L2224/05552 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/08145 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2225/06503 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2225/06555 ,  H01L2225/06562 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/14 ,  H01L2924/1436 ,  H01L2924/15311

Abstract: This application is directed to a stacked semiconductor device assembly including a plurality of identical stacked integrated circuit (IC) devices. Each IC device further includes a master interface, a channel master circuit, a slave interface, a channel slave circuit, a memory core, and a modal pad configured to receive a selection signal for the IC device to communicate data using one of its channel master circuit or its channel slave circuit. In some implementations, the IC devices include a first IC device and one or more second IC devices. In accordance with the selection signal, the first IC device is configured to communicate read/write data via the channel master circuit of the first IC device, and each of the one or more second IC devices is configured to communicate respective read/write data via the channel slave circuit of the respective second IC device.

公开(公告)号：US11887666B2

公开(公告)日：2024-01-30

申请号：US18146046

申请日：2022-12-23

Applicant: Zeno Semiconductor, Inc.

Inventor： Yuniarto Widjaja

IPC: G11C14/00 ,  G11C11/56 ,  H10B12/00 ,  H10B41/30 ,  H10B41/35 ,  G11C11/404 ,  H01L29/66 ,  H01L29/78 ,  H01L29/788 ,  H01L29/06 ,  H01L29/49 ,  G11C16/06 ,  H01L29/423 ,  G11C16/04

CPC classification number: G11C14/0018 ,  G11C11/404 ,  G11C11/565 ,  G11C16/06 ,  H01L29/0649 ,  H01L29/42328 ,  H01L29/4916 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/788 ,  H01L29/7841 ,  H01L29/7881 ,  H10B12/00 ,  H10B12/20 ,  H10B41/30 ,  H10B41/35 ,  G11C16/0416 ,  G11C16/0433 ,  G11C2211/4016

Abstract: A semiconductor memory cell includes a floating body region configured to be charged to a level indicative of a state of the memory cell; a first region in electrical contact with said floating body region; a second region in electrical contact with said floating body region and spaced apart from said first region; and a gate positioned between said first and second regions. The cell may be a multi-level cell. Arrays of memory cells are disclosed for making a memory device. Methods of operating memory cells are also provided.

公开(公告)号：US11776627B2

公开(公告)日：2023-10-03

申请号：US17573456

申请日：2022-01-11

Applicant: Rambus Inc.

Inventor： Aws Shallal ,  Nigel Alvares ,  Sarvagya Kochak

IPC: G06F12/0804 ,  G11C14/00 ,  G11C11/4076 ,  G11C11/4093

CPC classification number: G11C14/0018 ,  G06F12/0804 ,  G06F2212/1032 ,  G11C11/4076 ,  G11C11/4093

Abstract: A system that includes a non-volatile memory subsystem having non-volatile memory. The system also includes a plurality of memory modules that are separate from the non-volatile memory subsystem. Each memory module can include a plurality of random access memory packages where each first random access memory package includes a primary data port and a backup data port. Each memory module can include a storage interface circuit coupled to the backup data ports of the random access memory packages. The storage interface circuit offloads data from the memory module in the event of a power loss by receiving data from the backup data ports of the random access memory packages and transmitting the data to the non-volatile memory subsystem.