公开(公告)号：US20240304243A1

公开(公告)日：2024-09-12

申请号：US18119104

申请日：2023-03-08

Applicant: Crossbar, Inc.

Inventor： Zhi Li ,  Sung Hyun Jo ,  Jordan Frick

IPC: G11C13/00

CPC classification number: G11C13/0097 ,  G11C13/0033 ,  G11C13/004 ,  G11C13/0064 ,  G11C13/0069

Abstract: Improved erase techniques and apparatuses can improve performance and longevity of non-volatile memory. Various disclosed techniques include performing an erase operation(s) on a group of such memory cells, followed by a weak program operation. One or more subsequent erase-verify operations can be implemented until no erase disturb states are detected for the memory cells, or until a maximum erase-verify cycle count is reached. In one or more embodiments, additional weak program and erase-verify cycles can be implemented to enhance cycle longevity and reduce erase disturb states for the group of non-volatile memory.

公开(公告)号：US12020764B2

公开(公告)日：2024-06-25

申请号：US17735889

申请日：2022-05-03

Applicant: SK hynix Inc.

Inventor： Hyung-Sik Won ,  Hyungsup Kim

IPC: G11C8/00 ,  G11C13/00 ,  G11C16/30 ,  G11C16/34 ,  G11C29/00 ,  G11C29/44 ,  G11C29/52 ,  G11C29/04

CPC classification number: G11C29/783 ,  G11C13/0097 ,  G11C16/30 ,  G11C16/349 ,  G11C29/44 ,  G11C29/52 ,  G11C29/76 ,  G11C29/785 ,  G11C29/835 ,  G11C2029/0411 ,  G11C2207/2236

Abstract: A memory system includes a plurality of memory devices and a controller. Each of the memory devices includes a memory cell array, a sense amplifier for amplifying data stored in the memory cell array, a first memory cell sub-array included in the memory cell array directly coupled to the sense amplifier, a switch coupled to the first memory cell sub-array, and a second memory cell sub-array included in the memory cell array coupled to the sense amplifier through the first memory cell sub-array and the switch. When the switch is enabled, the memory device operates as a normal mode, and when the switch is disabled, the memory device operates as a fast mode faster than the normal mode. The controller dynamically sets a mode of each of the memory devices based on requests externally provided, by controlling the switch of each of the memory devices.

公开(公告)号：US11901032B2

公开(公告)日：2024-02-13

申请号：US17735860

申请日：2022-05-03

Applicant: SK hynix Inc.

Inventor： Hyung-Sik Won ,  Hyungsup Kim

IPC: G11C8/00 ,  G11C29/00 ,  G11C29/44 ,  G11C16/34 ,  G11C13/00 ,  G11C29/52 ,  G11C16/30 ,  G11C29/04

CPC classification number: G11C29/783 ,  G11C13/0097 ,  G11C16/30 ,  G11C16/349 ,  G11C29/44 ,  G11C29/52 ,  G11C29/76 ,  G11C29/785 ,  G11C29/835 ,  G11C2029/0411 ,  G11C2207/2236

Abstract: A memory system includes a memory device and a memory controller. The memory device includes a memory cell array including normal memory cells and redundancy memory cells suitable for replacing failed memory cell among the normal memory cells, and a device controller for activating reserved memory cells which are included in the redundancy memory cells and not used to replace the failed memory cell. The memory controller controls the memory device, when a first memory cells are accessed more than a threshold access number, to move data stored in the first memory cells to the reserved memory cells and replace the first memory cells with the reserved memory cells.

公开(公告)号：US20240005989A1

公开(公告)日：2024-01-04

申请号：US18468500

申请日：2023-09-15

Applicant: SK hynix Inc.

Inventor： In Ku KANG

IPC: G11C13/00

CPC classification number: G11C13/0069 ,  G11C13/0026 ,  G11C13/0097 ,  G11C13/0038 ,  G11C13/0028

Abstract: Provided herein may be a resistive memory device and a method of operating the resistive memory device. The resistive memory device may include strings coupled between one or more source lines and one or more bit lines, each string including a set of one or more resistive memory cells, one or more word lines respectively coupled to the set of one or more resistive memory cells; and a voltage generator configured to control a level of a turn-on voltage to be applied to one or more unselected word lines among the one or more word lines depending on a program target state of a subset of resistive memory cells including one or more resistive memory cells selected from among the set of one or more resistive memory cells.

公开(公告)号：US20230420044A1

公开(公告)日：2023-12-28

申请号：US18231053

申请日：2023-08-07

Applicant: Unisantis Electronics Singapore Pte. Ltd.

Inventor： Koji SAKUI ,  Nozomu HARADA

IPC: G11C13/00

CPC classification number: G11C13/0069 ,  G11C13/0038 ,  G11C13/0097

Abstract: A memory apparatus includes a page including a plurality of memory cells arranged in a column on a substrate. Each of voltages applied to first and second gate conductor layers and first and second impurity layers in each memory cell included in the page is controlled to perform a page write operation of retaining holes, which have been formed through an impact ionization phenomenon or using a gate induced drain leakage current, in a semiconductor base material, or each of voltages applied to the first and second gate conductor layers, third and fourth gate conductor layers, and the first and second impurity layers is controlled to perform a page erase operation of removing the holes from the semiconductor base material, and further lowering a voltage of the semiconductor base material through capacitive coupling with the first gate conductor layer and the second gate conductor layer.

公开(公告)号：US11848050B2

公开(公告)日：2023-12-19

申请号：US17829571

申请日：2022-06-01

Applicant: HEFEI RELIANCE MEMORY LIMITED

Inventor： Brent Steven Haukness

IPC: G11C13/00 ,  G11C8/08

CPC classification number: G11C13/0069 ,  G11C13/004 ,  G11C13/0007 ,  G11C13/0028 ,  G11C13/0097 ,  G11C8/08 ,  G11C2013/0045 ,  G11C2013/0071 ,  G11C2013/0078 ,  G11C2213/79

Abstract: The gate of the access transistor of a 1 transistor 1 resistor (1T1R) type RRAM cell is biased relative to the source of the access transistor using a current mirror. Under the influence of a voltage applied across the 1T1R cell (e.g., via the bit line), the RRAM memory element switches from a higher resistance to a lower resistance. As the RRAM memory element switches from the higher resistance to the lower resistance, the current through the RRAM cell switches from being substantially determined by the higher resistance of the RRAM device (while the access transistor is operating in the linear region) to being substantially determined by the saturation region operating point of the access transistor.

公开(公告)号：US20230368839A1

公开(公告)日：2023-11-16

申请号：US18315117

申请日：2023-05-10

Applicant: Commissariat à l'énergie atomique et aux énergies alternatives ,  Université d'Aix-Marseille ,  Centre national de la recherche scientifique

Inventor： Djohan BONNET ,  Tifenn HIRTZLIN ,  Elisa VIANELLO ,  Eduardo ESMANHOTTO ,  Jean-Michel PORTAL

IPC: G11C13/00

CPC classification number: G11C13/0069 ,  G11C13/004 ,  G11C13/0097

Abstract: A memory cell, includes first and second main terminals, an auxiliary terminal; M memristor(s) between the main terminals, M≥1; M primary switch(es), each in parallel with a memristor; and a secondary switch between the second main terminal and the auxiliary terminal. It is configured for writing to at least one memristor by opening each primary switch in parallel with the at least one memristor, closing each other primary switch, closing the secondary switch and applying a corresponding programming voltage between the first main terminal and the auxiliary terminal; and for reading at least one memristor by opening each primary switch in parallel with the at least one memristor, closing each other possible primary switch, opening the secondary switch and measuring a corresponding electrical quantity between the main terminals.

公开(公告)号：US11790989B2

公开(公告)日：2023-10-17

申请号：US17329008

申请日：2021-05-24

Applicant: Applied Materials, Inc.

Inventor： Deepak Kamalanathan ,  Siddarth Krishnan ,  Archana Kumar ,  Fuxi Cai ,  Federico Nardi

IPC: G11C11/00 ,  G11C13/00

CPC classification number: G11C13/0097 ,  G11C13/004 ,  G11C13/0038 ,  G11C13/0069

Abstract: A method for setting memory elements in a plurality of states includes applying a set signal to a memory element to transition the memory element from a low-current state to a high-current state; applying a partial reset signal to the memory element to transition the memory element from the high-current state to a state between the high-current state and the low-current state; determining whether the state corresponds to a predetermined state; and applying one or more additional partial reset signals to the memory element until the state corresponds to the predetermined current state. The memory element may be coupled in series with a transistor, and a voltage control circuit may apply voltages to the transistor to set and partially reset the memory element.

公开(公告)号：US20230306245A1

公开(公告)日：2023-09-28

申请号：US17703889

申请日：2022-03-24

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Jen-Chieh LIU ,  Win-San KHWA ,  Jui-Jen WU ,  Meng-Fan CHANG

IPC: G06N3/063 ,  G11C13/00 ,  G11C11/54

CPC classification number: G06N3/063 ,  G11C13/0004 ,  G11C13/0069 ,  G11C13/0061 ,  G11C13/0097 ,  G11C13/003 ,  G11C11/54 ,  G11C2213/79

Abstract: A programming circuit includes a time difference converter circuit and a pulse generator circuit. The converter circuit is configured to receive a first pulse from a first neuron device and a second pulse from a second neuron device, and to output a time difference signal corresponding to a time difference between the first pulse and the second pulse. The pulse generator circuit includes an input coupled to the output of the time difference converter circuit to receive the time difference signal, and an output at which the pulse generator circuit is configured to output a program voltage corresponding to the time difference signal. The output of the pulse generator circuit is configured to be coupled to a synapse device coupled between the first neuron device and the second neuron device to program a weight value in the synapse device with the program voltage.

公开(公告)号：US20230299772A1

公开(公告)日：2023-09-21

申请号：US17696473

申请日：2022-03-16

Applicant: Crossbar, Inc.

Inventor： Sang Nguyen ,  Cung Vu ,  Hagop Nazarian

IPC: H03K19/1776 ,  G11C13/00

CPC classification number: H03K19/1776 ,  G11C13/0069 ,  G11C13/0097

Abstract: A field programmable gate array (FPGA) utilizing resistive switching memory technology is described. The FPGA can comprise a switching block interconnect having a set of signal input lines and a set of signal output lines. Respective intersections of the signal input lines and signal output lines can have two resistive switching memory cells, a current differential latch, and a switching transistor (also referred to as a pass gate transistor) arranged in a circuit. Resistance states of the resistive switching memory cells can be programmed to control an output voltage state of the current differential latch. The output voltage state is latched into the current differential latch which can drive a gate of the switching transistor to activate or deactivate the switching transistor, which in turn activates or deactivates an intersection of the FPGA.