公开(公告)号：US20240347113A1

公开(公告)日：2024-10-17

申请号：US18752870

申请日：2024-06-25

申请人： KIOXIA CORPORATION

发明人： Yasuhiro SHIINO ,  Eietsu TAKAHASHI ,  Koki UENO

IPC分类号： G11C16/26 ,  G11C11/56 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/14 ,  G11C16/34

CPC分类号： G11C16/26 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/14 ,  G11C16/3427 ,  G11C16/349

摘要： A nonvolatile semiconductor memory device according to one embodiment of the present invention includes: a memory cell array and a control circuit. The control circuit executes a first reading operation and a second reading operation. The first reading operation is an operation of reading a threshold voltage set in the selected memory cell by setting a voltage between a control gate electrode and source of the selected memory cell to a first value. The second reading operation is an operation of reading a threshold voltage set in the selected memory cell by setting a voltage between the control gate electrode and source of the selected memory cell to a second value lower than the first value. When executing the second reading operation, the control circuit keeps a voltage of the control gate electrode of the selected memory cell to 0 or a positive value.

公开(公告)号：US12009038B2

公开(公告)日：2024-06-11

申请号：US17659897

申请日：2022-04-20

申请人： Micron Technology, Inc.

发明人： Rainer Frank Bonitz

IPC分类号： G11C16/10 ,  G11C16/04 ,  G11C16/16 ,  G11C16/26 ,  G11C16/34

CPC分类号： G11C16/349 ,  G11C16/0483 ,  G11C16/16 ,  G11C16/26 ,  G11C16/345

摘要： A controller of a memory device may determine that an endurance parameter associated with a wear leveling pool of a memory of the memory device satisfies a threshold. The wear leveling pool includes a plurality of memory blocks of the memory. The controller may divide, based on determining that the endurance parameter satisfies the threshold, the plurality of memory blocks of the wear leveling pool into a first wear leveling pool subset that includes a first subset of the plurality of memory blocks and a second wear leveling pool subset that includes a second subset of the plurality of memory blocks. A first subset of a plurality of data partitions is stored in the first subset of the plurality of memory blocks, and a second subset of the plurality of data partitions is stored in the second subset of the plurality of memory blocks.

公开(公告)号：US20240096420A1

公开(公告)日：2024-03-21

申请号：US18522829

申请日：2023-11-29

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： SUNG-MIN JOE

IPC分类号： G11C16/08 ,  G11C16/04 ,  G11C16/10 ,  G11C16/26 ,  G11C16/34 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H10B41/27 ,  H10B43/27

CPC分类号： G11C16/08 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/26 ,  G11C16/3459 ,  G11C16/349 ,  H01L24/16 ,  H01L25/0657 ,  H01L25/18 ,  H10B41/27 ,  H10B43/27 ,  H01L2224/08145 ,  H01L2924/1431 ,  H01L2924/14511

摘要： According to an exemplary embodiment of the inventive concept, there is provided a nonvolatile memory device comprising: a memory cell region including a first metal pad, a peripheral circuit region including a second metal pad and vertically connected to the memory cell region by the first metal pad and the second metal pad, a memory cell array, in the memory cell region, comprising a plurality of memory cells, a plurality of word lines and a bit line connected to the memory cells, wherein each memory cell is connected to one of the word lines, a voltage generator, in the peripheral circuit region, supplying a plurality of supply voltages to the memory cell array, a control logic circuit, in the peripheral circuit region, programming a selected one of the memory cells connected to a selected one of the word lines into a first program state by controlling the voltage generator, and a verify circuit, in the peripheral circuit region, controlling a verify operation on the memory cell array by controlling the voltage generator, wherein the verify circuit controls a word line voltage applied to at least one unselected word line not to be programmed among the plurality of word lines in the verify operation and a bit line voltage applied to the bit line connected differently from a voltage level of a voltage applied in a read operation of the nonvolatile memory device.

公开(公告)号：US20240096394A1

公开(公告)日：2024-03-21

申请号：US18513319

申请日：2023-11-17

申请人： Lodestar Licensing Group LLC

发明人： Dean D. Gans

IPC分类号： G11C11/406 ,  G11C16/34

CPC分类号： G11C11/40618 ,  G11C11/40615 ,  G11C16/349

摘要： A method of operating a memory device is provided, comprising determining a number of operations corresponding to a memory location during a first timing period; and scheduling an extra refresh operation for the memory location after the first timing period when the determined number of operations exceeds a predetermined threshold. A memory device is provided, comprising a memory including a memory location; and circuitry configured to: determine a number of operations corresponding to the memory location during a first timing period; and schedule an extra refresh operation for the memory location after the first timing period when the determined number of operations exceeds a predetermined threshold.

公开(公告)号：US20240071513A1

公开(公告)日：2024-02-29

申请号：US17893755

申请日：2022-08-23

申请人： Micron Technology, Inc.

发明人： Phil REUSSWIG

IPC分类号： G11C16/16 ,  G11C16/24 ,  G11C16/34

CPC分类号： G11C16/16 ,  G11C16/24 ,  G11C16/349

摘要： Aspects of the present disclosure configure a memory sub-system processor to manage memory erase operations. The processor accesses a configuration register to identify a quantity of memory slices to erase. The processor divides a set of memory components into a plurality of portions based on the identified quantity of memory slices to erase and performs one or more read operations in association with the memory sub-system between erasure of each of the plurality of portions of the set of memory components.

公开(公告)号：US11914885B2

公开(公告)日：2024-02-27

申请号：US17577213

申请日：2022-01-17

申请人： SK hynix Inc.

发明人： Dong Uk Lee ,  Hae Chang Yang ,  Hun Wook Lee

IPC分类号： G11C16/34 ,  G06F3/06 ,  G11C16/04 ,  G11C16/26 ,  G11C16/10 ,  G11C29/52 ,  G11C16/08 ,  G06F12/02 ,  G11C29/50

CPC分类号： G06F3/0653 ,  G06F3/064 ,  G06F3/0655 ,  G06F3/0679 ,  G06F12/0246 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C16/349 ,  G11C16/3427 ,  G11C16/3459 ,  G11C29/50004 ,  G11C29/52

摘要： The present disclosure provides a memory controller including a state detector detecting whether the memory device is in an idle state, a program controller, based on detection information that indicates a state of the memory device, selecting neighboring strings that are adjacent to a string that is coupled to a memory cell, among the memory cells, on which a program operation or a read operation was performed before the detecting, selecting monitoring memory cells that are coupled to at least one word line, the memory cells being a part of the neighboring strings, and controlling the memory device to perform a plurality of loops to program the monitoring memory cells, and a bad block selector selecting a memory block with the monitoring memory cells as a bad block based on a rate of increase in threshold voltage of a threshold voltage distribution of the monitoring memory cells.

公开(公告)号：US11894092B2

公开(公告)日：2024-02-06

申请号：US17325690

申请日：2021-05-20

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Myoungho Son ,  Wontaeck Jung ,  Buil Nam

IPC分类号： G11C29/50 ,  H01L25/18 ,  H01L23/00 ,  G11C11/56 ,  G11C16/04 ,  G11C16/08 ,  G11C16/16 ,  G11C16/34 ,  H01L25/065 ,  H10B41/27 ,  H10B43/27

CPC分类号： G11C29/50004 ,  G11C11/5635 ,  G11C11/5671 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/16 ,  G11C16/349 ,  H01L24/08 ,  H01L25/0657 ,  H01L25/18 ,  H10B41/27 ,  H10B43/27 ,  G11C2029/5004 ,  H01L2224/08145 ,  H01L2924/1431 ,  H01L2924/14511

摘要： A fail detecting method of a memory system including a nonvolatile memory device and a memory controller, the fail detecting method including: counting, by the memory controller, the number of erases of a word line connected to a pass transistor; issuing a first erase command, by the memory controller, when the number of erases reaches a reference value; applying a first voltage, by the nonvolatile memory device, in response to the first erase command, that causes a gate-source potential difference of the pass transistor to have a first value; detecting, by the memory controller, a leakage current in a word line, after the applying of the first voltage; and determining, by the memory controller, the word line as a fail when a leakage voltage caused by the leakage current is greater than a first threshold value.

公开(公告)号：US11886313B2

公开(公告)日：2024-01-30

申请号：US17026603

申请日：2020-09-21

申请人： Innogrit Technologies Co., Ltd.

发明人： Gang Zhao ,  Lin Chen ,  Wei Jiang ,  Jie Chen ,  Tao Wei

IPC分类号： G06F11/30 ,  G06F11/07 ,  G11C7/04 ,  G11C7/14 ,  G11C16/10 ,  G11C16/26 ,  G11C16/34

CPC分类号： G06F11/3037 ,  G06F11/076 ,  G06F11/3058 ,  G11C7/04 ,  G11C7/14 ,  G11C16/10 ,  G11C16/26 ,  G11C16/3404 ,  G11C16/349

摘要： Systems, apparatus and methods are provided for temperature assisted non-volatile storage device management in a non-volatile storage system. In one embodiment, a non-volatile storage system may comprise a temperature sensor, a non-volatile storage device and a processor. The processor may be configured to obtain a read-out from the temperature sensor, generate a predicted real-time on-die temperature for the non-volatile storage device based on the read-out, generate an estimated threshold voltage for reading data stored in the non-volatile storage device based on the predicted real-time on-die temperature and conduct a local sweep of a reference voltage using the estimated threshold voltage as a starting point to obtain a final read reference voltage with a minimum read bit error rate.

公开(公告)号：US20240029802A1

公开(公告)日：2024-01-25

申请号：US17871689

申请日：2022-07-22

申请人： Micron Technology, Inc.

发明人： Zhenming Zhou ,  Murong Lang ,  Li-Te Chang

IPC分类号： G11C16/34 ,  G11C11/406

CPC分类号： G11C16/3418 ,  G11C16/349 ,  G11C11/40618

摘要： An example system can include a memory device and a processing device. The memory device can include a group of memory cells. The processing device can be coupled to the memory device. The processing device can be configured to determine a distance of a memory die from a center of a memory component. The processing device can be configured to perform a read disturb operation on the memory die based on the determined distance use a first voltage window for a set of memory cells of the group of memory cells during a first time period.

公开(公告)号：US20230420053A1

公开(公告)日：2023-12-28

申请号：US17846452

申请日：2022-06-22

申请人： SanDisk Technologies LLC

发明人： Xuan Tian ,  Henry Chin ,  Liang Li ,  Vincent Yin ,  Wei Zhao ,  Tony Zou

IPC分类号： G11C16/14 ,  G11C16/04 ,  G11C16/24 ,  G11C16/08 ,  G11C16/26 ,  G11C16/34 ,  G11C29/50

CPC分类号： G11C16/14 ,  G11C16/0483 ,  G11C16/24 ,  G11C16/08 ,  G11C16/26 ,  G11C16/349 ,  G11C29/50004 ,  H01L27/11556

摘要： The memory device includes a memory block with an array of memory cells. The memory device also includes control circuitry that is in communication with the memory cells. The control circuitry is configured to program a group of the memory cells in a programming operation that does not include verify to obtain a natural threshold voltage (nVt) distribution, calculate an nVt width of the nVt distribution, compare the nVt width to a threshold, and identify the memory block as being vulnerable to cross-temperature read errors in response to the nVt width exceeding the threshold.