公开(公告)号：US12237426B2

公开(公告)日：2025-02-25

申请号：US17553109

申请日：2021-12-16

Applicant: KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGY

Inventor： Shinhyun Choi ,  Beomjin Kim ,  Tae Ryong Kim ,  See On Park

IPC: H01L29/788 ,  G06F17/16 ,  G11C16/14 ,  G11C16/24 ,  G11C16/26 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L29/792

Abstract: Provided is a floating gate based 3-terminal analog synapse device including a silicon channel layer; a gate oxide deposited on the silicon channel layer; a charge trap layer deposited on the gate oxide, wherein charges are injected into the charge trap layer; a barrier layer deposited on the charge trap layer, and having lower electron affinity than electron affinity of a material of the charge trap layer; and a gate metal layer deposited on an upper surface of the barrier layer, wherein a gate voltage is applied to the gate metal layer.

公开(公告)号：US12230326B2

公开(公告)日：2025-02-18

申请号：US17943487

申请日：2022-09-13

Applicant: Kioxia Corporation

Inventor： Keisuke Suda ,  Ryota Suzuki ,  Kenta Yamada

IPC: G11C16/06 ,  G11C5/02 ,  G11C16/04 ,  G11C16/14 ,  G11C16/26 ,  G11C16/34 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10 ,  H10B43/27

Abstract: A semiconductor memory device includes memory blocks arranged in a first direction and bit lines that are arranged in a second direction, and are arranged with the memory blocks in a third direction. The memory block includes first conductive layers arranged in the third direction, a second conductive layer disposed on a side opposite to the bit lines in the third direction with respect to the first conductive layers, semiconductor layers that extend in the third direction, are opposed to the first conductive layers, have one ends in the third direction electrically connected to the second conductive layer, and have the other ends in the third direction electrically connected to the bit lines, and electric charge accumulating films disposed between the first conductive layers and the semiconductor layers. The first conductive layers and the second conductive layer are separated between the memory blocks.

公开(公告)号：US12217802B2

公开(公告)日：2025-02-04

申请号：US17648311

申请日：2022-01-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jooyong Park ,  Sangwon Park ,  Dongjin Shin ,  Suchang Jeon ,  Seungyong Choi

IPC: G11C16/26 ,  G11C16/04 ,  G11C16/08 ,  G11C16/14 ,  G11C16/20

Abstract: A non-volatile memory device includes a meta area having a first region storing first initial data, and second regions storing second initial data, different from each other; a user area configured to store user data; an initialization register configured to store the first initial data or update the second initial data in whole or in part; and control logic configured to perform a read operation, a program operation, or an erase operation using the initial data stored in the initialization register.

公开(公告)号：US12211561B2

公开(公告)日：2025-01-28

申请号：US17899951

申请日：2022-08-31

Applicant: KIOXIA CORPORATION

Inventor： Takeshi Hioka

IPC: G11C16/28 ,  G11C16/04 ,  G11C16/14

Abstract: A semiconductor storage device includes a plurality of word line layers stacked above one another in a first direction, a memory pillar having a columnar body penetrating the plurality of the word line layers, wherein each portion of the memory pillar intersecting the word line layers functions as a memory cell transistor, a source line layer to which an end of the memory pillar is connected, an acquisition circuit configured to acquire a voltage of the source line layer, and a first adjustment circuit configured to adjust the voltage of the source line layer to a predetermined target voltage based on the acquired voltage. The acquisition circuit includes a dummy pillar having a columnar body penetrating the plurality of word line layers and having an end connected to the source line layer, wherein each portion of the dummy pillar intersecting the word line layers functions as a dummy transistor.

公开(公告)号：US12190958B2

公开(公告)日：2025-01-07

申请号：US17956225

申请日：2022-09-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jun-Ho Seo ,  Sang Yong Yoon ,  Min Soo Kim ,  Jeong Hoon Nam ,  Hyeon Su Bak

IPC: G11C5/00 ,  G11C16/14 ,  G11C16/26

Abstract: A storage device and an operating method of the storage device are provided. The storage device comprises a first non-volatile memory device, a second non-volatile memory device, a third non-volatile memory device a storage controller configured to control the first non-volatile memory device, the second non-volatile memory device, and the third non-volatile memory device, control the first non-volatile memory device to extract a first on-cell count value after a first soft erase operation, set first to third read level offsets of the respective first to third non-volatile memory devices based on the respective first to third on-cell count values, select the first to third defense code parameter sets each corresponding to the respective first to third read level offsets, and transmits first to third read commands based on the selected respective first to third defense code parameter sets to the respective first to third non-volatile memory devices.

公开(公告)号：US12176033B2

公开(公告)日：2024-12-24

申请号：US17951794

申请日：2022-09-23

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Zhipeng Dong ,  Ying Cui ,  Li Xiang

IPC: G11C16/04 ,  G11C16/08 ,  G11C16/14

Abstract: A memory device, an operating method thereof, a system, and a non-transitory tangible storage medium are disclosed. The memory device includes a source line (SL), a bit line (BL), a memory string, a word line, a select line and a peripheral circuit. The memory string includes a memory cell and a select transistor including a storage layer. The word line is coupled to the memory cell. The select line is coupled to the select transistor. The peripheral circuit is coupled to the SL, the BL, the select line, and the word line. The peripheral circuit is configured to: apply a first voltage to the select line; and apply a second voltage to the SL and/or the BL, in which a first peak level of the first voltage is greater than a second peak level of second voltage.

公开(公告)号：US12170115B2

公开(公告)日：2024-12-17

申请号：US17451479

申请日：2021-10-19

Applicant: Micron Technology, Inc.

Inventor： Meng Wei

IPC: G11C16/14 ,  G06F12/02 ,  G11C16/16 ,  G11C16/32

Abstract: Exemplary methods, apparatuses, and systems include erasing a portion of memory from a garbage pool in response to detecting an idle period. A request to write data to the memory is received and it is determined that a charge gain threshold has not been satisfied for the erased portion of memory. The data is written to the erased portion of memory in response to determining the charge gain threshold has not been satisfied.

公开(公告)号：US20240404603A1

公开(公告)日：2024-12-05

申请号：US18401467

申请日：2023-12-30

Applicant: Nuvoton Technology Corporation

Inventor： Wei-Ling LIN ,  Chia-Hao HUANG ,  Tsun-Yao FAN

IPC: G11C16/22 ,  G11C16/14

Abstract: A control circuit including a storage circuit, a register, and a write protection logic circuit is provided. The storage circuit stores data, an enable-set value and a mode-set value. The register stores a protection-set value. The write protection logic circuit determines whether to change at least one of the enable-set value, the mode-set value, and the protection-set value according to the mode-set value after receiving a write command. In response to the mode-set value matching a pre-determined value, the write protection logic circuit changes at least one of the enable-set value, the mode-set value, and the protection-set value according to the protection-set value. In response to the mode-set value not matching the pre-determined value, the write protection logic circuit does not change the enable-set value and the mode-set value.

公开(公告)号：US12148478B2

公开(公告)日：2024-11-19

申请号：US17952846

申请日：2022-09-26

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Masaaki Higashitani ,  Abhijith Prakash ,  Dengtao Zhao

IPC: G11C16/14 ,  G11C16/04 ,  G11C16/34 ,  H01L25/065

Abstract: A non-volatile memory system comprises a plurality of non-volatile memory cells divided into three or more tiers. The memory cells can be programmed, erased and read. In order to achieve uniform erase speed for the three or more tiers, the erase process comprises applying a larger voltage bias to control gates of non-volatile memory cells in the outer tiers than the voltage bias applied to control gates of non-volatile memory cells in one or more inner tiers.

公开(公告)号：US12148474B2

公开(公告)日：2024-11-19

申请号：US17561656

申请日：2021-12-23

Applicant: Micron Technology, Inc.

Inventor： Akira Goda ,  Shafqat Ahmed ,  Khaled Hasnat ,  Krishna K. Parat

IPC: G11C16/04 ,  G11C16/06 ,  G11C16/10 ,  G11C16/12 ,  G11C16/14 ,  G11C16/26 ,  G11C16/34 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10 ,  H10B43/27

Abstract: Apparatus and methods are disclosed, such as an apparatus that includes a string of charge storage devices associated with a pillar (e.g., of semiconductor material), a source gate device, and a source select device coupled between the source gate device and the string. Additional apparatus and methods are described.