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    MEMORY DEVICES THAT SUPPORT SELECTIVE SETTING DATA UPDATE AND METHODS OF OPERATING SAME
    2.
    发明公开
    MEMORY DEVICES THAT SUPPORT SELECTIVE SETTING DATA UPDATE AND METHODS OF OPERATING SAME 审中-公开

    公开(公告)号：US20240231697A1

    公开(公告)日：2024-07-11

    申请号：US18469931

    申请日：2023-09-19

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Keeho Jung ,  Suchang Jeon

    IPC: G06F3/06

    CPC classification number: G06F3/0659 ,  G06F3/0607 ,  G06F3/0653 ,  G06F3/0679

    Abstract: A memory device includes a memory cell array having a plurality of cell blocks therein, including at least one cell block configured to store information data read (IDR) data related to setting an operating environment of the memory device. A setting data storage circuit is provided, which includes a plurality of storage regions in which the IDR data, which is read from the at least one cell block, is stored and a reset operation is independently controlled. Control logic is provided, which is configured to control at least one of a reset operation on the setting data storage circuit, and an IDR operation of updating the IDR data to the setting data storage circuit according to a decoding result of an external command. The control logic is configured to selectively reset only some storage regions of the setting data storage circuit in response to a determination that the external command is a first reset command, but reset all storage regions of the setting data storage circuit in response to a determination that the external command is a second reset command.

    NONVOLATILE MEMORY DEVICE AND MEMORY SYSTEM
    3.
    发明申请
    NONVOLATILE MEMORY DEVICE AND MEMORY SYSTEM 有权

    公开(公告)号：US20250103513A1

    公开(公告)日：2025-03-27

    申请号：US18601839

    申请日：2024-03-11

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Hanjun Lee ,  Suyong Kim ,  Seungjae Lee ,  Suchang Jeon

    IPC: G06F12/14 ,  G06F3/06

    Abstract: A nonvolatile memory device includes a memory cell array to store an original setting data, a page buffer circuit connected to the memory cell array through a plurality of bit-lines, a secure buffer and a control circuit. The secure buffer includes an access control circuit and a plurality registers with restricted access, and the plurality registers store the original setting data that is dumped-down from the memory cell array through the page buffer circuit in an initialization sequence. The control circuit controls the page buffer circuit and the secure buffer. The plurality registers include a first register and second registers. The access control circuit, in response to the first register being accessed, accesses at least a portion of the second registers concurrently with accessing the first register.

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