公开(公告)号：US12190954B2

公开(公告)日：2025-01-07

申请号：US17817408

申请日：2022-08-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hanjun Lee ,  Byungsoo Kim ,  Sangwan Nam

IPC: G11C16/10 ,  G11C16/04 ,  G11C16/34

Abstract: A program method includes applying a first voltage to a plurality of bit lines, applying a second voltage to a common source line (CSL), and performing a program loop by applying a program voltage and a verify voltage to each of a plurality of ground selection lines (GSLs) positioned between one bit line among the plurality of bit lines and the CSL. The program loop is performed on both a program completed cell in which a program is completed by applying the program voltage and a program target cell.

公开(公告)号：US20250103513A1

公开(公告)日：2025-03-27

申请号：US18601839

申请日：2024-03-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hanjun Lee ,  Suyong Kim ,  Seungjae Lee ,  Suchang Jeon

IPC: G06F12/14 ,  G06F3/06

Abstract: A nonvolatile memory device includes a memory cell array to store an original setting data, a page buffer circuit connected to the memory cell array through a plurality of bit-lines, a secure buffer and a control circuit. The secure buffer includes an access control circuit and a plurality registers with restricted access, and the plurality registers store the original setting data that is dumped-down from the memory cell array through the page buffer circuit in an initialization sequence. The control circuit controls the page buffer circuit and the secure buffer. The plurality registers include a first register and second registers. The access control circuit, in response to the first register being accessed, accesses at least a portion of the second registers concurrently with accessing the first register.

公开(公告)号：US20230096057A1

公开(公告)日：2023-03-30

申请号：US17817408

申请日：2022-08-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hanjun Lee ,  Byungsoo Kim ,  Sangwan Nam

IPC: G11C16/10 ,  G11C16/04 ,  G11C16/34

Abstract: A program method includes applying a first voltage to a plurality of bit lines, applying a second voltage to a common source line (CSL), and performing a program loop by applying a program voltage and a verify voltage to each of a plurality of ground selection lines (GSLs) positioned between one bit line among the plurality of bit lines and the CSL. The program loop is performed on both a program completed cell in which a program is completed by applying the program voltage and a program target cell.