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公开(公告)号：US20240363190A1
公开(公告)日：2024-10-31
申请号：US18771393
申请日：2024-07-12
发明人： Li-Te Chang , Yu-Chung Lien , Murong Lang , Zhenming Zhou , Michael G. Miller
CPC分类号： G11C29/52 , G11C16/08 , G11C16/102 , G11C16/3404
摘要： An example method of performing memory access operations comprises: receiving a request to perform a memory access operation; identifying a block family associated with a set of memory cells; determining, for each logical programming level of a plurality of logical programming levels, a corresponding default block family error avoidance (BFEA) threshold voltage offset value associated with the block family; determining a value of a data state metric associated with the set of memory cells; determining, for each logical programming level of a plurality of logical programming levels, a corresponding sub-BFEA threshold voltage offset value; and performing the memory access operation by applying, for each logical programming level of the plurality of logical programming levels, a combination of the default BFEA threshold voltage value, the sub-BFEA threshold voltage value, and a corresponding base voltage level.
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公开(公告)号：US20240363169A1
公开(公告)日：2024-10-31
申请号：US18765164
申请日：2024-07-05
发明人： Kaiwei Li , Jianquan Jia , Hongtao Liu , An Zhang
CPC分类号： G11C16/14 , G11C16/3445 , G11C16/0483
摘要： A memory device includes a memory string and a control circuit. The memory string includes a top select gate, a memory cell, and a bottom select gate. The top select gate is coupled to a first select line, the memory cell is coupled to a word line, and the bottom select gate is coupled to a second select line. The control circuit is coupled to the first select line, the word line, and the second select line. The control circuit is configured to, in an erasing operation comprising an erasing stage and a verification stage after the erasing stage, apply an erasing voltage to the memory string in the erasing stage, apply a first voltage to the word line in a first stage of the verification stage, apply a second voltage lower than the first voltage to the word line in a second stage after the first stage, apply a first turn-on voltage to the second select line before applying the second voltage to the word line, and apply a second turn-on voltage to the first select line after stopping application of the erasing voltage for a period of time.
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公开(公告)号：US20240363167A1
公开(公告)日：2024-10-31
申请号：US18227175
申请日：2023-07-27
发明人： Sisi Yang , Yanjie Wang
CPC分类号： G11C16/102 , G11C16/0433 , G11C16/14 , G11C16/3459
摘要： A memory apparatus and method of operation are provided. The apparatus includes memory cells each connected to one of a plurality of word lines and disposed in memory holes. The memory cells are configured to retain a threshold voltage corresponding to one of a plurality of data states. A control means is coupled to the plurality of word lines and the memory holes and is configured to program the memory cells in a program operation. During the program operation, the control means programs the memory cells connected to at least one particular word line of the plurality of word lines using a first programming technique while programming the memory cells connected to plurality of word lines other than the at least one particular word line using a second programming technique different than the first programming technique.
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公开(公告)号：US12131790B2
公开(公告)日：2024-10-29
申请号：US18125595
申请日：2023-03-23
IPC分类号： G06F11/10 , G06F3/06 , G06F11/34 , G06F12/02 , G06F12/0891 , G06F16/11 , G06F16/16 , G06F16/17 , G11C16/10 , G11C16/16 , G11C16/26 , G11C16/34
CPC分类号： G11C16/3495 , G06F12/0891 , G11C16/102 , G11C16/16 , G11C16/26 , G06F2212/1016 , G06F2212/7201 , G06F2212/7211
摘要： A method includes determining that a ratio of valid data portions to a total quantity of data portions of a block of memory cells is greater than or less than a valid data portion threshold and determining that health characteristics for the valid data portions of the block of memory cells are greater than or less than a valid data health characteristic threshold. The method further includes performing a first media management operation on the block of memory cells in response to determining that the ratio of valid data portions to the total quantity of data portions is greater than the valid data portion threshold and performing a second media management operation on at least a portion of the block of memory cells in response to determining that the ratio of valid data portions to the total quantity of data portions is less than the valid data portion threshold and the health characteristics for the valid data portions are greater than the valid data health characteristic threshold.
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5.发明公开公开(公告)号：US20240355400A1
公开(公告)日：2024-10-24
申请号：US18346347
申请日：2023-07-03
发明人： Abu Naser Zainuddin , Mark Shlick , Jiahui Yuan
CPC分类号： G11C16/3459 , G11C16/0433 , G11C16/102 , G11C16/32
摘要： To reduce spikes in the current used during read operations by a system of multiple NAND memory dies operated in parallel, relative delays between the memory dies are introduced before high current sub-operations of the read. The occurrence of the primary current peak in the read operation can depend upon the extent to which a selected memory block is programmed. For example, in a closed block the primary peak occurs when ramping up unselected word lines, while for an open block the primary read peak occurs when the bit lines are charged up. To account for these differences, determining where to introduce relative delays is based on the extent to which a block is programmed. For example, if a block fully or largely closed, delays are introduced before ramping up the unselected word lines, but otherwise adding the delays before charging up bit lines.
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公开(公告)号：US20240355399A1
公开(公告)日：2024-10-24
申请号：US18226191
申请日：2023-07-25
发明人： Zhipeng Dong , Li Xiang , Zhuo Chen , Shuai Wang , Chunyuan Hou
CPC分类号： G11C16/3445 , G11C16/16
摘要： Implementations of the present disclosure provide a memory device, an operation method thereof, and a memory system. The memory device may include a memory cell array including a plurality of blocks. The memory device may include a peripheral circuit coupled to the memory cell array. The peripheral circuit may be configured to apply a plurality of different erasure verification voltages to a selected block among the plurality of blocks after applying a first effective erasure voltage to the selected block. The peripheral circuit may be configured to determine a second effective erasure voltage applied to the selected block according to a plurality of erasure verification results corresponding to the plurality of different erasure verification voltages. The second effective erasure voltage may be greater than the first effective erasure voltage.
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公开(公告)号：US12125536B2
公开(公告)日：2024-10-22
申请号：US17703625
申请日：2022-03-24
申请人： SK hynix Inc.
发明人： Chan Hui Jeong , Dong Hun Kwak , Se Chun Park
CPC分类号： G11C16/08 , G11C16/10 , G11C16/30 , G11C16/3459 , G11C16/0483
摘要： The present disclosure relates to an electronic device. A memory device includes a plurality of memory cells coupled to a plurality of word lines, a voltage generator generating program-related voltages to be applied to the plurality of word lines, an address decoder transferring the program-related voltages to the plurality of word lines, and an operation controller controlling the voltage generator and the address decoder to apply a program voltage to a selected word line among the plurality of word lines, a second pass voltage to adjacent word lines neighboring the selected word line, a first pass voltage to remaining word lines except for the selected word line and the adjacent word lines, and to apply a ground voltage to the selected word line and the first pass voltage to the adjacent word lines during a first period.
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公开(公告)号：US20240347118A1
公开(公告)日：2024-10-17
申请号：US18319501
申请日：2023-05-18
CPC分类号： G11C16/3459 , G11C16/102
摘要： A memory device and an enhance programming method thereof are provided. The enhance programming method includes: performing program and verifying operations on a plurality of memory cell groups of a memory division, where each of the memory cell group corresponds to at least one byte; calculating a programming time for completing program operation of each of the memory cell groups; setting an indication flag when the programming time is larger than a preset threshold value; and, when the indication flag is in a setting state, increasing at least one of a plurality of program operation parameters, and performing an enhancement programming operation on the memory cell groups of the memory division.
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9.发明授权公开(公告)号：US12119046B2
公开(公告)日：2024-10-15
申请号：US18045541
申请日：2022-10-11
发明人： Jaeduk Yu , Yohan Lee , Yonghyuk Choi , Jiho Cho
IPC分类号： G11C16/34 , G11C11/4074 , G11C11/408 , G11C11/4096
CPC分类号： G11C11/4085 , G11C11/4074 , G11C11/4096
摘要： A nonvolatile memory device having a multi-stack memory block includes: a memory cell array divided into a plurality of memory stacks disposed in a vertical direction; and a control circuit configured to perform a channel voltage equalization operation of the plurality of memory stacks, wherein inter-stack portions are between the plurality of memory stacks, and a channel hole passes through the word lines of each of the plurality of memory stacks. The control circuit determines, as inter-stack word lines, some word lines adjacent to the inter-stack portions among the word lines of each of the plurality of memory stacks and differently controls setup time points for applying a pass voltage, or recovery time points for applying a ground voltage, to the inter-stack word lines, according to sizes of the channel hole of the inter-stack word lines.
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公开(公告)号：US20240339160A1
公开(公告)日：2024-10-10
申请号：US18746964
申请日：2024-06-18
申请人： Kioxia Corporation
发明人： Tokumasa HARA , Noboru SHIBATA
CPC分类号： G11C16/26 , G11C16/08 , G11C16/102 , G11C16/30 , G11C16/3404
摘要： According to one embodiment, a semiconductor memory includes: a memory group including a plurality of memory cells configured to store a plurality of bits of data in three or more plurality of states; a word line coupled to the plurality of memory cells; and a first circuit configured to convert one external address received from an external controller into a plurality of internal addresses, wherein a first page size of page data of the memory group is smaller than a second page size of input data corresponding to the external address.
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