公开(公告)号：US20240194274A1

公开(公告)日：2024-06-13

申请号：US18531872

申请日：2023-12-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yonghyuk Choi ,  Jaeduk Yu ,  Yohan Lee

IPC: G11C16/34 ,  G11C16/04 ,  G11C16/08 ,  G11C16/28

CPC classification number: G11C16/3404 ,  G11C16/0433 ,  G11C16/08 ,  G11C16/28

Abstract: A memory device includes a word line area that is between a bit line and a common source line. The word line area includes a plurality of stacks. A first area includes first stacks with a first resistance value in the word line area, a second area includes second stacks with a second resistance value in the word line area, wherein the second resistance value is different from the first resistance value, a third area includes third stacks with a third resistance value that different from the first resistance value, and a processor is configured to control a recovery sequence of the first area, the second area, and the third area.

公开(公告)号：US20230013747A1

公开(公告)日：2023-01-19

申请号：US17935502

申请日：2022-09-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yonghyuk Choi ,  Sangwan Nam ,  Jaeduk Yu ,  Sangwon Park ,  Bongsoon Lim

IPC: G06F11/20 ,  G11C16/04 ,  G11C16/08

Abstract: A nonvolatile memory device includes a first semiconductor layer, a second semiconductor layer and a control circuit. The memory cell array includes a first vertical structure on the first upper substrate and a second vertical structure on the second upper substrate, the first vertical structure includes first sub-blocks and the second vertical structure includes second sub-blocks. The second semiconductor layer includes a lower substrate that includes address decoders and page buffer circuits. The first vertical structure includes first via areas in which one or more through-hole vias are provided, through-hole vias pass through the first vertical structure. The first sub-blocks are arranged among the first via areas and the second sub-blocks are arranged among the second via areas. The control circuit groups the memory blocks into a plurality of groups based on whether the memory blocks is close to the first via areas and performs address re-mapping.

公开(公告)号：US11501847B2

公开(公告)日：2022-11-15

申请号：US17022967

申请日：2020-09-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yonghyuk Choi ,  Sangwan Nam ,  Jaeduk Yu ,  Sangwon Park ,  Bongsoon Lim

IPC: G11C16/10 ,  G11C29/00 ,  G11C29/44 ,  G11C29/18 ,  G11C7/10 ,  G11C29/12

Abstract: A nonvolatile memory device includes memory cell region including a first metal pad and a peripheral circuit region including a second metal pad, is connected to the memory cell region by the first metal pad and the second metal pad and includes including an address decoder and a page buffer circuit located on a first substrate. A memory cell array is provided in the memory cell region, which includes a first vertical structure on a second substrate. The first vertical structure includes first sub-blocks and first via areas in which one or more through-hole vias are provided, and through-hole vias pass through the first vertical structure. A control circuit in the peripheral circuit region groups the memory blocks into a plurality of groups based on whether the memory blocks is close to the first via areas and performs address re-mapping.

公开(公告)号：US11467932B2

公开(公告)日：2022-10-11

申请号：US16865948

申请日：2020-05-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yonghyuk Choi ,  Sangwan Nam ,  Jaeduk Yu ,  Sangwon Park ,  Bongsoon Lim

IPC: G11C16/10 ,  G06F11/20 ,  G11C16/04 ,  G11C16/08 ,  H01L27/11556 ,  H01L27/11582

Abstract: A nonvolatile memory device includes a first semiconductor layer, a second semiconductor layer and a control circuit. The memory cell array includes a first vertical structure on the first upper substrate and a second vertical structure on the second upper substrate, the first vertical structure includes first sub-blocks and the second vertical structure includes second sub-blocks. The second semiconductor layer includes a lower substrate that includes address decoders and page buffer circuits. The first vertical structure includes first via areas in which one or more through-hole vias are provided, through-hole vias pass through the first vertical structure. The first sub-blocks are arranged among the first via areas and the second sub-blocks are arranged among the second via areas. The control circuit groups the memory blocks into a plurality of groups based on whether the memory blocks is close to the first via areas and performs address re-mapping.

公开(公告)号：US12057391B2

公开(公告)日：2024-08-06

申请号：US17933770

申请日：2022-09-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yohan Lee ,  Chaehoon Kim ,  Jaeduk Yu ,  Jiho Cho

IPC: H01L27/115 ,  H01L23/522 ,  H10B43/27

CPC classification number: H01L23/5226 ,  H10B43/27

Abstract: A semiconductor device includes a CSL driver on a substrate, a CSP on the CSL driver, a gate electrode structure on the CSP and including gate electrodes spaced apart from each other in a first direction perpendicular to an upper surface of the substrate, each of the gate electrodes extends in a second direction parallel to the upper surface of the substrate, a memory channel structure on the CSP and extending through the gate electrode structure and is connected to the CSP, a first upper wiring structure contacting an upper surface of the CSP, a first through via extending through the CSP in the first direction and is electrically connected to the first upper wiring structure and the CSL driver but does not contact the CPS, and a dummy wiring structure contacting the upper surface of the CSP but is not electrically connected to the CSL driver.

公开(公告)号：US20240221836A1

公开(公告)日：2024-07-04

申请号：US18515848

申请日：2023-11-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yohan Lee ,  Jaeduk Yu ,  Sangsoo Park ,  Jonghoon Park

IPC: G11C16/08 ,  G11C16/04 ,  G11C16/10 ,  G11C16/12

CPC classification number: G11C16/08 ,  G11C16/0433 ,  G11C16/102 ,  G11C16/12

Abstract: A method of operating a memory device, the method includes applying a pass voltage to a plurality of word lines during a word line setup period, applying an on-voltage to an unselected ground select line at a first time point during the word line setup period, increasing a voltage of the plurality of word lines by applying a pre-charge voltage to the common source line at a second time point during the word line setup period, applying an off-voltage to the unselected ground select line at a third time point during the word line setup period, and applying a ground voltage to the common source line at a fourth time point during the word line setup period.

公开(公告)号：US20230170031A1

公开(公告)日：2023-06-01

申请号：US18159882

申请日：2023-01-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yonghyuk CHOI ,  Sangwan Nam ,  Jaeduk Yu ,  Yohan Lee

IPC: G11C16/34 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18

CPC classification number: G11C16/3427 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24 ,  H01L24/08 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/08145 ,  H01L2924/1431 ,  H01L2924/14511 ,  H10B41/27

Abstract: A nonvolatile memory device includes at least one memory block and a control circuit. The at least one memory block includes a plurality of cell strings, each including a string selection transistor, a plurality of memory cells and a ground selection transistor. The control circuit controls a program operation by precharging channels of the plurality of cell strings to a first voltage during a bit-line set-up period of a program loop, applying a program voltage to a selected word-line of the plurality of cell strings during a program execution period of the program loop and after recovering voltages of the selected word-line and unselected word-lines of the plurality of cell strings to a negative voltage smaller than a ground voltage, recovering the voltages of the selected word-line and the unselected word-lines to a second voltage greater than the ground voltage during a recovery period of the program loop.

公开(公告)号：US11200002B2

公开(公告)日：2021-12-14

申请号：US16918310

申请日：2020-07-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yonghyuk Choi ,  Jaeduk Yu ,  Sangwan Nam ,  Sangwon Park ,  Daeseok Byeon ,  Bongsoon Lim

IPC: G06F3/00 ,  G06F3/06 ,  G11C16/08 ,  G11C16/24 ,  G11C16/04 ,  H01L27/11556 ,  H01L27/11582

Abstract: A nonvolatile memory device includes a first semiconductor layer including an upper substrate in which word-lines extending in a first direction and bit-lines extending in a second direction are disposed and a memory cell array, a second semiconductor layer, a control circuit, and a pad region. The memory cell array includes a vertical structure on the upper substrate, and the vertical structure includes memory blocks. The second semiconductor layer includes a lower substrate that includes address decoders and page buffer circuits. The vertical structure includes via areas in which one or more through-hole vias are provided, and the via areas are spaced apart in the second direction. The memory cell array includes mats corresponding to different bit-lines of the bit-lines. At least two of the mats include a different number of the via areas according to a distance from the pad region in the first direction.

公开(公告)号：US20240249794A1

公开(公告)日：2024-07-25

申请号：US18394640

申请日：2023-12-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaeyun Lee ,  Makoto Hirano ,  Sangsoo Park ,  Jaeduk Yu

IPC: G11C29/52 ,  G11C7/10 ,  G11C29/02

CPC classification number: G11C29/52 ,  G11C7/106 ,  G11C29/022

Abstract: A memory device according to an embodiment includes a memory cell array including a plurality of memory cells, a control logic configured to control a verification operation for the plurality of memory cells, a page buffer block including a plurality of page buffers connected to the memory cell array through bit lines, a page buffer decoder that outputs, through an output line. a verification signal generated from at least one of outputs of the plurality of page buffers by a verification operation, and a verification error removal circuit connected to the output line and configured to control an output path of the verification signal to the control logic.

公开(公告)号：US11854623B2

公开(公告)日：2023-12-26

申请号：US17520276

申请日：2021-11-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaeduk Yu ,  Dongkyo Shim

IPC: G11C16/16 ,  G06F12/02 ,  G06F3/06 ,  G11C16/34

CPC classification number: G11C16/16 ,  G06F3/064 ,  G06F12/0246 ,  G11C16/3431 ,  G11C16/3436 ,  G06F3/0679 ,  G06F2212/7211

Abstract: Provided are a memory controller and memory system having an improved threshold voltage distribution characteristic and an operating method of the memory system. As a write request of data with respect to a first block is received, an erase program interval (EPI) is determined denoting a time period elapsed after erasure of the first block. When the determined EPI is equal to or less than a reference time, data is programmed to the first block based on a first operation condition selected from among a plurality of operation conditions. When the determined EPI is greater than the reference time, the data is programmed to the first block based on a second operation condition selected from among the plurality of operation conditions.