公开(公告)号：US11948640B2

公开(公告)日：2024-04-02

申请号：US17371568

申请日：2021-07-09

Applicant: Kioxia Corporation

Inventor： Makoto Iwai ,  Hiroshi Nakamura

IPC: G11C11/34 ,  G11C11/56 ,  G11C16/04 ,  G11C16/06 ,  G11C16/08 ,  G11C16/26 ,  G11C16/34

CPC classification number: G11C16/0483 ,  G11C11/56 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C16/06 ,  G11C16/08 ,  G11C16/26 ,  G11C16/3436 ,  G11C16/3454 ,  G11C16/3459

Abstract: A memory includes first and second select gate transistors, memory cells, a source line, a bit line, a selected word line which is connected to a selected memory cell as a target of a verify reading, a non-selected word line which is connected to a non-selected memory cell except the selected memory cell, a potential generating circuit for generating a selected read potential which is supplied to the selected word line, and generating a non-selected read potential larger than the selected read potential, which is supplied to the non-selected word line, and a control circuit which classifies a threshold voltage of the selected memory cell to one of three groups by verifying which area among three area which are isolated by two values does a cell current of the selected memory cell belong, when the selected read potential is a first value.

公开(公告)号：US20240006001A1

公开(公告)日：2024-01-04

申请号：US18369479

申请日：2023-09-18

Applicant: Micron Technology, Inc.

Inventor： Eric N. Lee ,  Dheeraj Srinivasan

IPC: G11C16/34 ,  G11C16/26 ,  G11C7/10 ,  G11C16/10

CPC classification number: G11C16/3436 ,  G11C16/26 ,  G11C7/1084 ,  G11C7/1057 ,  G11C16/10

Abstract: A system includes a memory component and a processing device, operatively coupled with the memory component, to send a read command to the memory component while a program or erase operation being executed by the memory component is suspended. The processing device, operatively coupled with the memory component, can then send an auto resume command to the memory component to automatically resume execution of the program or erase operation after the read command is executed.

公开(公告)号：US11749345B2

公开(公告)日：2023-09-05

申请号：US17393027

申请日：2021-08-03

Applicant: SK hynix Inc.

Inventor： Sang Heon Lee

IPC: G11C16/08 ,  G11C16/26 ,  G11C11/4074 ,  G11C16/16 ,  G11C16/34 ,  G11C16/12

CPC classification number: G11C16/08 ,  G11C11/4074 ,  G11C16/12 ,  G11C16/16 ,  G11C16/26 ,  G11C16/3436

Abstract: The present technology includes a memory device and a method of operating the memory device. The memory device includes a memory block including a plurality of memory cells connected to word lines, peripheral circuits configured to generate operation voltages to be applied to the word lines, and control logic configured to control the peripheral circuits in response to a program command, a read command, or an erase command. The peripheral circuits include a voltage generator that adjusts a section of threshold voltage distributions of memory cells to be programmed among the memory cells, according to a distance between the word lines.

公开(公告)号：US20230252265A1

公开(公告)日：2023-08-10

申请号：US18126233

申请日：2023-03-24

Applicant: Silicon Storage Technology, Inc. ,  The Regents of the University of California

Inventor： Farnood Merrikh Bayat ,  Xinjie Guo ,  Dmitri Strukov ,  Nhan Do ,  Hieu Van Tran ,  Vipin Tiwari ,  Mark Reiten

IPC: G06N3/04 ,  G06N3/063 ,  G11C11/54 ,  G11C16/34 ,  G11C29/38 ,  G06N3/045 ,  G11C16/08 ,  G11C16/12 ,  G11C16/16 ,  G06F3/06

CPC classification number: G06N3/04 ,  G06N3/063 ,  G11C11/54 ,  G11C16/3436 ,  G11C29/38 ,  G06N3/045 ,  G11C16/08 ,  G11C16/12 ,  G11C16/16 ,  G06F3/061 ,  G06F3/0655 ,  G06F3/0688

Abstract: A method of scanning N×N pixels using a vector-by-matrix multiplication array by (a) associating a filter of M×M pixels adjacent first vertical and horizontal edges, (b) providing values for the pixels associated with different respective rows of the filter to input lines of different respective N input line groups, (c) shifting the filter horizontally by X pixels, (d) providing values for the pixels associated with different respective rows of the horizontally shifted filter to input lines, of different respective N input line groups, which are shifted by X input lines, (e) repeating steps (c) and (d) until a second vertical edge is reached, (f) shifting the filter horizontally to be adjacent the first vertical edge, and shifting the filter vertically by X pixels, (g) repeating steps (b) through (e) for the vertically shifted filter, and (h) repeating steps (f) and (g) until a second horizontal edge is reached.

公开(公告)号：US20180342305A1

公开(公告)日：2018-11-29

申请号：US15926419

申请日：2018-03-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SANG-SOO CHA ,  YOUNG-SEOP SHIM ,  DAE-WON KIM

IPC: G11C16/34 ,  G11C16/26 ,  G06F13/16 ,  G06F13/40

CPC classification number: G11C16/3404 ,  G06F13/1673 ,  G06F13/4068 ,  G11C11/5642 ,  G11C13/0033 ,  G11C13/0035 ,  G11C13/004 ,  G11C16/26 ,  G11C16/3418 ,  G11C16/3436 ,  G11C16/3495 ,  G11C2013/0057

Abstract: A method of operating a storage device includes: performing a background read operation on a nonvolatile memory by using a default read voltage level; performing a read retry operation on the nonvolatile memory by using a corrected read voltage level when the background read operation fails; storing the corrected read voltage level in a history buffer when the read retry operation succeeds; and performing a host read operation on the nonvolatile memory by using the history buffer in response to a read request received from a host.

公开(公告)号：US10074439B2

公开(公告)日：2018-09-11

申请号：US15174667

申请日：2016-06-06

Applicant: SK hynix Inc.

Inventor： Haibo Li ,  Shi Yin ,  Lingqi Zeng ,  Yu Cai ,  Fan Zhang ,  June Lee

IPC: G11C16/04 ,  G11C16/34 ,  G11C7/02 ,  G11C11/56 ,  G11C16/10 ,  G11C29/04

CPC classification number: G11C16/3431 ,  G11C7/02 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3427 ,  G11C16/3436 ,  G11C2029/0411

Abstract: Memory systems may include a memory including a plurality of wordlines, each wordline including a plurality of cells, and a controller suitable for obtaining an initial voltage threshold and a target state for each of the plurality of cells, applying a pulse based on a pulse value to the plurality of cells, and calculating at least one coupling effect to neighboring cells.

公开(公告)号：US20180075910A1

公开(公告)日：2018-03-15

申请号：US15606798

申请日：2017-05-26

Applicant: SK hynix Inc.

Inventor： Jin Yong SEONG

IPC: G11C16/10 ,  G11C16/04 ,  G11C16/34 ,  G11C16/26 ,  G11C16/30 ,  G11C16/08 ,  G11C16/24 ,  G11C11/34 ,  G11C11/063

CPC classification number: G11C16/10 ,  G06F13/16 ,  G11C7/1063 ,  G11C11/063 ,  G11C11/34 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/22 ,  G11C16/24 ,  G11C16/26 ,  G11C16/30 ,  G11C16/3436

Abstract: Provided herein are a semiconductor memory device and a method of operating the same. The semiconductor memory device includes a memory cell array including a plurality of memory cells, a status signal generator configured to output an internal status signal indicating whether an operation of the memory cell array has been completed or is being performed and a ready/busy line input mode control unit configured to output a ready/busy signal through a ready/busy line based on the internal status signal or to receive an input signal from an external device through the ready/busy line.

公开(公告)号：US20180024948A1

公开(公告)日：2018-01-25

申请号：US15458561

申请日：2017-03-14

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Wanfang Tsai ,  Yan Li

IPC: G06F13/16 ,  G06F5/06 ,  G11C16/34 ,  G06F3/06 ,  G11C16/04 ,  G11C16/10

CPC classification number: G06F13/1673 ,  G06F3/061 ,  G06F3/0655 ,  G06F3/0688 ,  G06F5/065 ,  G06F13/1642 ,  G06F2205/067 ,  G06F2212/2022 ,  G06F2212/7203 ,  G11C7/1039 ,  G11C7/106 ,  G11C7/1066 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3427 ,  G11C16/3436 ,  G11C16/3454 ,  G11C29/84

Abstract: Systems and methods for controlling data flow and data alignment using data expand and compress circuitry arranged between a variable data rate bi-directional first in, first out (FIFO) buffer and one or more memory arrays to compensate for bad column locations within the one or more memory arrays are described. The bi-directional FIFO may have a variable data rate with the array side and a fixed data rate with a serializer/deserializer (SERDES) circuit that drives input/output (I/O) circuitry. The data expand and compress circuitry may pack and unpack data and then align the data passing between the one or more memory arrays and the bi-directional FIFO using a temporary buffer, data shuffling logic, and selective pipeline stalls.

公开(公告)号：US09857992B2

公开(公告)日：2018-01-02

申请号：US15076963

申请日：2016-03-22

Applicant: Intel Corporation

Inventor： Kiran Pangal ,  Ravi J. Kumar

IPC: G11C29/02 ,  G11C29/50 ,  G11C29/10 ,  G11C29/04 ,  G06F3/06 ,  G06F11/10 ,  G06F11/20 ,  G11C11/56 ,  G11C16/14 ,  G11C16/26 ,  G11C16/34 ,  G11C29/52 ,  G11C16/00

CPC classification number: G06F3/0616 ,  G06F3/064 ,  G06F3/0653 ,  G06F3/0659 ,  G06F3/0679 ,  G06F11/1068 ,  G06F11/2094 ,  G11C11/5635 ,  G11C11/5642 ,  G11C16/00 ,  G11C16/14 ,  G11C16/26 ,  G11C16/3436 ,  G11C29/021 ,  G11C29/026 ,  G11C29/028 ,  G11C29/50016 ,  G11C29/52 ,  G11C2029/0401

Abstract: Methods and apparatus to provide dynamic window to improve NAND (Not And) memory endurance are described. In one embodiment, a program-erase window associated with a NAND memory device is dynamically varied by starting with a higher erase verify (TEV) voltage and lowering the TEV voltage with subsequent cycles over a life of the NAND memory device based on a current cycle count value. Alternatively, the program-erase window is dynamically varied by starting with a higher erase verify (PV) voltage and erase verify (TEV) voltage and lowering the PV and TEV voltages with subsequent cycles over a life of the NAND memory device based on the current cycle count value. Other embodiments are also disclosed and claimed.

公开(公告)号：US09620228B1

公开(公告)日：2017-04-11

申请号：US15078416

申请日：2016-03-23

Applicant: Marvell International Ltd.

Inventor： Amey Dattatray Inamdar

IPC: G11C16/04 ,  G11C16/16

CPC classification number: G11C16/16 ,  G11C16/04 ,  G11C16/105 ,  G11C16/3436

Abstract: A monotonically increasing persistent counter is described that is persistent across reboots of a system in which it is incorporated. The described counter employs an event counter module that counts events that are generated by various event generators within the system. One type of event that can be counted by the described counter is a state change. In various implementations, the event counter module, when employed as a state change counter module, includes a state change counter that counts state changes, and a journal mode component which provides journaling functionality which makes it possible to accommodate large numbers of state changes while, at the same time, recover the counter in the event of a system failure. In at least some embodiments, one or both of the state change counter and the journal mode component are implemented using NOR flash memory.