公开(公告)号：US11295823B2

公开(公告)日：2022-04-05

申请号：US16909418

申请日：2020-06-23

Applicant: KIOXIA CORPORATION

Inventor： Hiroshi Nakamura ,  Kenichi Imamiya ,  Toshio Yamamura ,  Koji Hosono ,  Koichi Kawai

IPC: G11C7/10 ,  G11C16/34 ,  G11C7/06 ,  G11C16/10 ,  G11C16/26 ,  G06F3/06 ,  G06F12/02 ,  G11C16/06 ,  G11C16/08

Abstract: In a semiconductor integrated circuit, an internal circuit is capable of executing a first operation and a second operation concurrently, and an output circuit outputs to the outside of the semiconductor integrated circuit information indicating whether or not the first operation is being executed and information indicating whether or not the second operation is executable.

公开(公告)号：US11705204B2

公开(公告)日：2023-07-18

申请号：US17585370

申请日：2022-01-26

Applicant: KIOXIA CORPORATION

Inventor： Masanobu Shirakawa ,  Takuya Futatsuyama ,  Kenichi Abe ,  Hiroshi Nakamura ,  Keisuke Yonehama ,  Atsuhiro Sato ,  Hiroshi Shinohara ,  Yasuyuki Baba ,  Toshifumi Minami

IPC: G11C16/00 ,  G11C16/14 ,  G11C16/04 ,  G11C11/56 ,  H10B43/27 ,  H10B43/35 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C29/42 ,  G11C16/34

CPC classification number: G11C16/14 ,  G11C11/5635 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C29/42 ,  H10B43/27 ,  H10B43/35 ,  G11C16/3445

Abstract: A semiconductor memory device includes a first memory cell, a second memory cell above the first memory cell, a first word line electrically connected to a gate of the first memory cell, a second word line electrically connected to a gate of the second memory cell, and a control unit that performs an erasing operation on the first and second memory cells. During the erasing operation, the control unit applies a first voltage to a first word line and a second voltage higher than the first voltage to a second word line.

公开(公告)号：US11270773B2

公开(公告)日：2022-03-08

申请号：US17103504

申请日：2020-11-24

Applicant: KIOXIA CORPORATION

Inventor： Masanobu Shirakawa ,  Takuya Futatsuyama ,  Kenichi Abe ,  Hiroshi Nakamura ,  Keisuke Yonehama ,  Atsuhiro Sato ,  Hiroshi Shinohara ,  Yasuyuki Baba ,  Toshifumi Minami

IPC: G11C16/00 ,  G11C16/14 ,  G11C16/04 ,  H01L27/1157 ,  H01L27/11582 ,  G11C11/56 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C29/42 ,  G11C16/34

Abstract: A semiconductor memory device includes a first memory cell, a second memory cell above the first memory cell, a first word line electrically connected to a gate of the first memory cell, a second word line electrically connected to a gate of the second memory cell, and a control unit that performs an erasing operation on the first and second memory cells. During the erasing operation, the control unit applies a first voltage to a first word line and a second voltage higher than the first voltage to a second word line.

公开(公告)号：US11948640B2

公开(公告)日：2024-04-02

申请号：US17371568

申请日：2021-07-09

Applicant: Kioxia Corporation

Inventor： Makoto Iwai ,  Hiroshi Nakamura

IPC: G11C11/34 ,  G11C11/56 ,  G11C16/04 ,  G11C16/06 ,  G11C16/08 ,  G11C16/26 ,  G11C16/34

CPC classification number: G11C16/0483 ,  G11C11/56 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C16/06 ,  G11C16/08 ,  G11C16/26 ,  G11C16/3436 ,  G11C16/3454 ,  G11C16/3459

Abstract: A memory includes first and second select gate transistors, memory cells, a source line, a bit line, a selected word line which is connected to a selected memory cell as a target of a verify reading, a non-selected word line which is connected to a non-selected memory cell except the selected memory cell, a potential generating circuit for generating a selected read potential which is supplied to the selected word line, and generating a non-selected read potential larger than the selected read potential, which is supplied to the non-selected word line, and a control circuit which classifies a threshold voltage of the selected memory cell to one of three groups by verifying which area among three area which are isolated by two values does a cell current of the selected memory cell belong, when the selected read potential is a first value.

公开(公告)号：US11705443B2

公开(公告)日：2023-07-18

申请号：US17012111

申请日：2020-09-04

Applicant: Kioxia Corporation

Inventor： Hiroshi Maejima ,  Katsuaki Isobe ,  Nobuaki Okada ,  Hiroshi Nakamura ,  Takahiro Tsurudo

IPC: H01L25/18 ,  G11C16/04 ,  G11C16/08 ,  G11C16/26 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L25/18 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/26 ,  H01L24/08 ,  H01L25/0657 ,  H01L2224/08145 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: A semiconductor memory device according to an embodiment includes a substrate, a first memory cell, a first bit line, a first word line, a first transistor, and a second transistor. The first memory cell is provided above the substrate. The first bit line extends in a first direction. The first bit line is coupled to the first memory cell. The first word line extends in a second direction intersecting the first direction. The first word line is coupled to the first memory cell. The first transistor is provided on the substrate. The first transistor is coupled to the first bit line. The second transistor is provided below the first memory cell and on the substrate. The second transistor is coupled to the first word line.