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公开(公告)号：US12100453B2
公开(公告)日：2024-09-24
申请号：US17498686
申请日：2021-10-11
Applicant: Nuvoton Technology Corporation
Inventor： Bal S. Sandhu , Paul Vande Voorde , Chang-Xian Wu
IPC: H01L23/522 , G11C11/56 , G11C16/04 , G11C27/00 , H10B41/30
CPC classification number: G11C16/045 , G11C11/5635 , G11C27/005 , H01L23/5223 , H10B41/30
Abstract: A floating-node memory device includes a metal-oxide-semiconductor (MOS) transistor including a first polysilicon gate, a source region, and a drain region in a first well region, a tunneling device including a second polysilicon gate in a second well region, and a metal-insulator-metal (MIM) capacitor including a conductive top plate and a bottom plate formed in a metal interconnect layer. The floating-node device includes a floating-node comprising the first polysilicon gate, the second polysilicon gate, and the conductive top plate of the MIM capacitor coupled together, a control node at the bottom plate of the MIM capacitor, an erase node in the second well region, a source node at the source region of the MOS transistor, and a drain node at the drain region of the MOS transistor.
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公开(公告)号：US11967370B1
公开(公告)日：2024-04-23
申请号：US18390193
申请日：2023-12-20
Applicant: Vervain, LLC
Inventor： G. R. Mohan Rao
CPC classification number: G11C11/5635 , G06F11/1068 , G06F11/1072 , G06F12/0246 , G11C11/5621 , G11C11/5678 , G11C16/16 , G11C16/3495 , G11C29/52 , G11C29/76 , G06F2212/7202 , G11C2211/5641
Abstract: A controller for managing at least one MLC non-volatile memory space including at least one MLC non-volatile memory element and at least one SLC non-volatile memory space including at least one SLC non-volatile memory element. The controller is adapted to determine if a range of addresses listed by an entry and mapped to the at least one MLC non-volatile memory element fails a data integrity test performed at the controller based upon received data retained at the controller and which received data is stored in the at least one MLC memory element as stored data. In the event of such a failure, the controller remaps said entry to an the at least one SLC non-volatile memory element.
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公开(公告)号：US11967369B2
公开(公告)日：2024-04-23
申请号：US18387546
申请日：2023-11-07
Applicant: Vervain, LLC
Inventor： G. R. Mohan Rao
CPC classification number: G11C11/5635 , G06F11/1068 , G06F11/1072 , G06F12/0246 , G11C11/5621 , G11C11/5678 , G11C16/16 , G11C16/3495 , G11C29/52 , G11C29/76 , G06F2212/7202 , G11C2211/5641
Abstract: A flash controller for managing at least one MLC non-volatile memory module and at least one SLC non-volatile memory module. The flash controller is adapted to determine if a range of addresses listed by an entry and mapped to said at least one MLC nonvolatile memory module fails a data integrity test. In the event of such a failure, the controller remaps said entry to an equivalent range of addresses of said at least one SLC non-volatile memory module. The flash controller is further adapted to determine which of the blocks in the MIX and SLC nonvolatile memory modules are accessed most frequently and allocating those blocks that receive frequent writes to the SLC non-volatile memory module and those blocks that receive infrequent writes to the MLC non-volatile memory module.
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公开(公告)号：US11923012B2
公开(公告)日：2024-03-05
申请号：US17962302
申请日：2022-10-07
Applicant: KIOXIA CORPORATION
Inventor： Hiroshi Maejima
CPC classification number: G11C16/10 , G06F3/0614 , G06F3/0631 , G06F3/0652 , G06F3/0659 , G06F3/0665 , G06F3/0679 , G06F12/0246 , G11C11/5635 , G11C16/0483 , G11C16/16 , G11C16/3418 , G06F2212/1032 , G06F2212/152 , G06F2212/214 , G06F2212/7202 , G11C2213/71
Abstract: A semiconductor storage device includes memory cells, select transistors, memory strings, first and second blocks, word lines, and select gate lines. In the memory string, the current paths of plural memory cells are connected in series. When data are written in a first block, after a select gate line connected to the gate of a select transistor of one of the memory strings in the first block is selected, the data are sequentially written in the memory cells in the memory string connected to the selected select gate line. When data are written in the second block, after a word line connected to the control gates of memory cells of different memory strings in the second block is selected, the data are sequentially written in the memory cells of the different memory strings in the second block which have their control gates connected to the selected word line.
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公开(公告)号：US11915756B2
公开(公告)日：2024-02-27
申请号：US17734359
申请日：2022-05-02
Applicant: KIOXIA CORPORATION
Inventor： Yasuhiro Shiino , Eietsu Takahashi
IPC: G11C16/00 , G11C16/04 , G11C11/56 , G11C16/16 , G11C16/34 , G11C16/10 , G11C16/14 , G11C16/08 , G11C16/28
CPC classification number: G11C16/0483 , G11C11/5635 , G11C16/08 , G11C16/10 , G11C16/14 , G11C16/16 , G11C16/28 , G11C16/3404 , G11C16/344 , G11C16/3413 , G11C16/3445 , G11C16/3463 , G11C2211/5621
Abstract: A nonvolatile semiconductor memory device includes a control circuit configured to control a soft program operation of setting nonvolatile memory cells to a first threshold voltage distribution state of the nonvolatile memory cells. When a characteristic of the nonvolatile memory cells is in a first state, the control circuit executes the soft program operation by applying a first voltage for setting the nonvolatile memory cells to the first threshold voltage distribution state to first word lines, and applying a second voltage higher than the first voltage to a second word line. When the characteristic of the nonvolatile memory cells is in a second state, the control circuit executes the soft program operation by applying a third voltage equal to or lower than the first voltage to the first word lines and applying a fourth voltage lower than the second voltage to the second word line.
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公开(公告)号：US11830546B2
公开(公告)日：2023-11-28
申请号：US17203385
申请日：2021-03-16
Applicant: VERVAIN, LLC
Inventor： G. R. Mohan Rao
CPC classification number: G11C11/5635 , G06F11/1068 , G06F11/1072 , G06F12/0246 , G11C11/5621 , G11C11/5678 , G11C16/16 , G11C16/3495 , G11C29/52 , G11C29/76 , G06F2212/7202 , G11C2211/5641
Abstract: A flash controller for managing at least one MLC non-volatile memory module and at least one SLC non-volatile memory module. The flash controller is adapted to determine if a range of addresses listed by an entry and mapped to said at least one MLC non-volatile memory module fails a data integrity test. In the event of such a failure, the controller remaps said entry to an equivalent range of addresses of said at least one SLC non-volatile memory module. The flash controller is further adapted to determine which of the blocks in the MLC and SLC non-volatile memory modules are accessed most frequently and allocating those blocks that receive frequent writes to the SLC non-volatile memory module and those blocks that receive infrequent writes to the MLC non-volatile memory module.
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7.发明授权
公开(公告)号：US11755899B2
公开(公告)日：2023-09-12
申请号：US16751202
申请日：2020-01-23
Applicant: Silicon Storage Technology, Inc.
Inventor： Hieu Van Tran , Steven Lemke , Vipin Tiwari , Nhan Do , Mark Reiten
IPC: G11C16/04 , G06N3/065 , G06F17/16 , G11C16/10 , G11C16/34 , G11C16/26 , G11C11/56 , G11C16/14 , G06N3/044
CPC classification number: G06N3/065 , G06F17/16 , G06N3/044 , G11C11/5628 , G11C11/5635 , G11C16/0425 , G11C16/10 , G11C16/14 , G11C16/26 , G11C16/3459 , G11C2216/04
Abstract: Numerous embodiments of a precision programming algorithm and apparatus are disclosed for precisely and quickly depositing the correct amount of charge on the floating gate of a non-volatile memory cell within a vector-by-matrix multiplication (VMM) array in an artificial neural network. Selected cells thereby can be programmed with extreme precision to hold one of N different values.
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公开(公告)号：US11733873B2
公开(公告)日：2023-08-22
申请号：US15829590
申请日：2017-12-01
Applicant: Micron Technology, Inc.
Inventor： Zoltan Szubbocsev
CPC classification number: G06F3/0616 , G06F3/0649 , G06F3/0688 , G06F12/10 , G11C11/005 , G11C16/3486 , G11C16/3495 , G06F2212/2022 , G06F2212/657 , G11C11/5635 , G11C16/16
Abstract: A computer storage device having: a host interface; a controller; non-volatile storage media having memory units of different types and having different program erase budgets; and firmware. The firmware instructs the controller to: generate an address map mapping logical addresses to physical addresses of the memory units the different types; and adjust the address map based at least in part on the program erase budgets to level wear across the memory units of the different types.
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公开(公告)号：US20230245697A1
公开(公告)日：2023-08-03
申请号：US18131511
申请日：2023-04-06
Applicant: Kioxia Corporation
Inventor： Noboru SHIBATA
CPC classification number: G11C11/5635 , G11C11/5642 , G11C16/3459 , G11C16/10 , G11C11/5628 , G11C16/0483
Abstract: According to one embodiment, a semiconductor memory device includes a memory cell array, a data storage circuit and a control circuit. The data storage circuit holds first data to be written into the memory cell and holds 1 bit data calculated from the first data. The control circuit writes the data of n bits into the memory cell in a first write operation and then executes a second write operation. The control circuit carries out the following control in the second write operation. It reads data stored in the memory cell in the first write operation. It restores the first data based on the data read from the memory cell and the 1 bit data held in the data storage circuit. It writes the restored first data into the memory cell.
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10.发明授权
公开(公告)号：US11699485B2
公开(公告)日：2023-07-11
申请号：US17408414
申请日：2021-08-21
Applicant: Samsung Electronics Co., Ltd.
Inventor： Ho-Sung Ahn , Youn-Soo Cheon
CPC classification number: G11C11/5628 , G06F3/0604 , G06F3/0659 , G06F3/0673 , G11C11/5635 , G11C11/5671 , G11C16/0483 , G11C16/10 , G11C16/14 , G11C16/30
Abstract: Provided herein are a nonvolatile memory device and a method of programming the same. The nonvolatile memory device includes a memory cell array including a plurality of word lines having a first word line and a plurality of memory cells connected to the first word line. The plurality of memory cells includes a plurality of monitoring cells and a plurality of data cells each data cell configured to store N-bit data, N being a natural number. The nonvolatile memory device is configured to perform a first program on the plurality of data cells and a detection program different from the first program on the one or more monitoring cells after performing the first program.
