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    Deep learning accelerator and random access memory with a camera interface
    1.
    发明授权
    Deep learning accelerator and random access memory with a camera interface 有权

    公开(公告)号：US11942135B2

    公开(公告)日：2024-03-26

    申请号：US17729830

    申请日：2022-04-26

    申请人： Micron Technology, Inc.

    发明人： Poorna Kale ,  Jaime Cummins

    IPC分类号： G11C11/34 ,  G06F9/30 ,  G06F9/38 ,  G06F9/50 ,  G06N3/063 ,  H04N23/69 ,  H04N23/80

    CPC分类号： G11C11/34 ,  G06F9/30007 ,  G06F9/3893 ,  G06F9/5027 ,  G06N3/063 ,  H04N23/69 ,  H04N23/80

    摘要： Systems, devices, and methods related to a Deep Learning Accelerator and memory are described. An integrated circuit may be configured to execute instructions with matrix operands and configured with: random access memory configured to store instructions executable by the Deep Learning Accelerator and store matrices of an Artificial Neural Network; a connection between the random access memory and the Deep Learning Accelerator; a first interface to a memory controller of a Central Processing Unit; and a second interface to an image generator, such as a camera. While the Deep Learning Accelerator is using the random access memory to process current input to the Artificial Neural Network in generating current output from the Artificial Neural Network, the Deep Learning Accelerator may concurrently load next input from the camera into the random access memory; and at the same time, the Central Processing Unit may concurrently retrieve prior output from the random access memory.

    MEMORY SYSTEM AND METHOD FOR OPERATING THE SAME
    3.
    发明申请
    MEMORY SYSTEM AND METHOD FOR OPERATING THE SAME 审中-公开

    公开(公告)号：US20180107597A1

    公开(公告)日：2018-04-19

    申请号：US15653990

    申请日：2017-07-19

    申请人： SK hynix Inc.

    发明人： Sang-Gu JO ,  Yong-Ju KIM

    IPC分类号： G06F12/0804 ,  G06F13/16 ,  G11C29/44 ,  G06F12/06 ,  G11C11/34 ,  G11C11/407

    CPC分类号： G06F12/0804 ,  G06F12/06 ,  G06F13/1647 ,  G06F13/1668 ,  G11C11/34 ,  G11C11/407 ,  G11C29/4401 ,  G11C29/72 ,  G11C29/83

    摘要： A memory system includes: a memory device; and a memory controller suitable for controlling the memory device, and the memory device includes: a plurality of normal memory cells; a plurality of redundant memory cells; and a soft repair circuit suitable for replacing a portion of normal memory cells among the plurality of the normal memory cells with the plurality of the redundant memory cells, and the memory controller controls the soft repair circuit to repair the portion of the normal memory cells among the plurality of the normal memory cells with the plurality of the redundant memory cells, commands the memory device to write a secure data in the plurality of the redundant memory cells, and controls the soft repair circuit to recover the repairing of the portion of the normal memory cells with the plurality of the redundant memory cells.

    Multiple programming pulse per loop programming and verification method for non-volatile memory devices
    8.
    发明授权
    Multiple programming pulse per loop programming and verification method for non-volatile memory devices 有权
    多重编程脉冲每循环编程和非易失性存储器件的验证方法

    公开(公告)号：US09466389B2

    公开(公告)日：2016-10-11

    申请号：US14570721

    申请日：2014-12-15

    申请人： SK hynix Inc.

    发明人： Jung Ryul Ahn

    IPC分类号： G11C16/34 ,  G11C16/10 ,  G11C11/56 ,  G11C16/12 ,  G11C11/34

    CPC分类号： G11C16/34 ,  G11C11/34 ,  G11C11/5628 ,  G11C16/10 ,  G11C16/12 ,  G11C16/3481

    摘要： A semiconductor device includes a memory block including memory cells connected to a word line, and an operation circuit suitable for consecutively applying a main program pulse and a sub program pulse to the word line to perform a program operation of the memory cells, and suitable for performing a program verification operation of the memory cells, wherein the sub program pulse has a lower voltage level than the main program pulse.

    摘要翻译： 一种半导体器件包括：存储单元，包括连接到字线的存储器单元;以及操作电路，适合于连续地将一个主程序脉冲和一个子程序脉冲施加到该字线以执行存储单元的编程操作，并且适用于 执行存储单元的程序验证操作，其中子程序脉冲具有比主程序脉冲更低的电压电平。