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    REFRESH OPERATION IN MULTI-DIE MEMORY
    1.
    发明公开
    REFRESH OPERATION IN MULTI-DIE MEMORY 审中-公开

    公开(公告)号：US20240170035A1

    公开(公告)日：2024-05-23

    申请号：US18373120

    申请日：2023-09-26

    Applicant: Lodestar Licensing Group LLC

    Inventor： Matthew A. Prather ,  Thomas H. Kinsley

    IPC: G11C11/406 ,  G11C7/10 ,  G11C11/407

    CPC classification number: G11C11/40611 ,  G11C7/1072 ,  G11C11/407

    Abstract: Methods, apparatuses, and systems for staggering refresh operations to memory arrays in different dies of a three-dimensional stacked (3DS) memory device are described. A 3DS memory device may include one die or layer of that controls or regulates commands, including refresh commands, to other dies or layers of the memory device. For example, one die of the 3DS memory may delay a refresh command when issuing the multiple concurrent memory refreshes would cause some problematic performance condition, such as high peak current, within the memory device.

    MEMORY DEVICE WITH SOURCE LINE CONTROL
    5.
    发明公开
    MEMORY DEVICE WITH SOURCE LINE CONTROL 审中-公开

    公开(公告)号：US20230386536A1

    公开(公告)日：2023-11-30

    申请号：US18232542

    申请日：2023-08-10

    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

    Inventor： Perng-Fei Yuh ,  Yih Wang

    IPC: G11C7/10 ,  G11C8/08 ,  G11C7/12

    CPC classification number: G11C7/1096 ,  G11C8/08 ,  G11C7/12 ,  G11C7/1069 ,  G11C11/407

    Abstract: Disclosed herein are related to a memory device including a set of memory cells and a memory controller. In one aspect, each of the set of memory cells includes a select transistor and a storage element connected in series between a corresponding bit line and a corresponding source line. In one aspect, the memory controller is configured to apply a first write voltage to a bit line coupled to a selected memory cell, apply a second write voltage to a word line coupled to a gate electrode of a select transistor of the selected memory cell during a first time period, and apply a third write voltage to a source line coupled to the selected memory cell. The second write voltage may be between the first write voltage and the third write voltage.

    MEMORY SYSTEM AND METHOD FOR OPERATING THE SAME
    7.
    发明申请
    MEMORY SYSTEM AND METHOD FOR OPERATING THE SAME 审中-公开

    公开(公告)号：US20180107597A1

    公开(公告)日：2018-04-19

    申请号：US15653990

    申请日：2017-07-19

    Applicant: SK hynix Inc.

    Inventor： Sang-Gu JO ,  Yong-Ju KIM

    IPC: G06F12/0804 ,  G06F13/16 ,  G11C29/44 ,  G06F12/06 ,  G11C11/34 ,  G11C11/407

    CPC classification number: G06F12/0804 ,  G06F12/06 ,  G06F13/1647 ,  G06F13/1668 ,  G11C11/34 ,  G11C11/407 ,  G11C29/4401 ,  G11C29/72 ,  G11C29/83

    Abstract: A memory system includes: a memory device; and a memory controller suitable for controlling the memory device, and the memory device includes: a plurality of normal memory cells; a plurality of redundant memory cells; and a soft repair circuit suitable for replacing a portion of normal memory cells among the plurality of the normal memory cells with the plurality of the redundant memory cells, and the memory controller controls the soft repair circuit to repair the portion of the normal memory cells among the plurality of the normal memory cells with the plurality of the redundant memory cells, commands the memory device to write a secure data in the plurality of the redundant memory cells, and controls the soft repair circuit to recover the repairing of the portion of the normal memory cells with the plurality of the redundant memory cells.

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