公开(公告)号：US20240145010A1

公开(公告)日：2024-05-02

申请号：US18404827

申请日：2024-01-04

Applicant: Micron Technology, Inc.

Inventor： Zhongguang Xu ,  Nicola Ciocchini ,  Zhenlei Shen ,  Charles See Yeung Kwong ,  Murong Lang ,  Ugo Russo ,  Niccolo' Righetti

IPC: G11C16/10 ,  G11C16/08 ,  G11C16/26 ,  G11C16/34

CPC classification number: G11C16/102 ,  G11C16/08 ,  G11C16/26 ,  G11C16/3481

Abstract: A processing device in a memory sub-system initiates a partial block handling protocol for a closed block of a memory device, the block comprising a plurality of wordlines. The processing device further sends a first programming command to the memory device to program one or more wordlines of the block with first padding data having a first data pattern, wherein the one or more wordlines are adjacent to a last wordline of the block programmed before the block was closed. In addition, the processing device sends a second programming command to the memory device to program all of a set of remaining wordlines of the block with second padding data having a second data pattern comprising fewer bits of data per cell than the first data pattern.

公开(公告)号：US11791003B2

公开(公告)日：2023-10-17

申请号：US17960252

申请日：2022-10-05

Applicant: Micron Technology, Inc.

Inventor： Kalyan Chakravarthy Kavalipurapu ,  George Matamis ,  Yingda Dong ,  Chang H. Siau

IPC: G11C16/10 ,  G11C16/34 ,  G11C16/26 ,  G11C16/30

CPC classification number: G11C16/3481 ,  G11C16/10 ,  G11C16/26 ,  G11C16/30 ,  G11C16/3404

Abstract: A memory device includes a memory array of memory cells and control logic, operatively coupled with the memory array. The control logic is to perform operations, which include causing the memory cells to be programmed with an initial voltage distribution representing multiple logical states; causing the memory cells to be programmed with a subsequent voltage distribution representing a subset of the multiple logical states at a higher voltage than that of the initial voltage distribution, wherein the subset of the multiple logical states is compacted above a program verify voltage level for the subsequent voltage distribution; and causing a first program verify operation of the subsequent voltage distribution to be performed on the memory cells to verify one or more voltage levels of the subsequent voltage distribution.

公开(公告)号：US11721403B2

公开(公告)日：2023-08-08

申请号：US17164795

申请日：2021-02-01

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： XiangNan Zhao ,  Yali Song ,  An Zhang ,  Hongtao Liu ,  Lei Jin

IPC: G11C16/06 ,  G11C16/34 ,  G11C11/56 ,  G11C16/08 ,  G11C16/12

CPC classification number: G11C16/3481 ,  G11C11/5628 ,  G11C16/08 ,  G11C16/12 ,  G11C16/3459 ,  G11C2211/5621

Abstract: When programming and verifying a memory device which includes a plurality of memory cells and a plurality of word lines, a first coarse programming is first performed on a first memory cell among the plurality of memory cells which is controlled by a first word line among the plurality of word lines, and then a second coarse programming is performed on a second memory cell among the plurality of memory cells which is controlled by a second word line among the plurality of word lines. Next, a first coarse verify current is used for determining whether the first memory cell passes a coarse verification and a second coarse verify current is used for determining whether the second memory cell passes a second coarse verification, wherein the second coarse verify current is smaller than the first coarse verify current.

公开(公告)号：US20230238067A1

公开(公告)日：2023-07-27

申请号：US18125714

申请日：2023-03-23

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： XiangNan Zhao ,  Yali Song ,  An Zhang ,  Hongtao Liu ,  Lei Jin

IPC: G11C16/34 ,  G11C11/56 ,  G11C16/08 ,  G11C16/12

CPC classification number: G11C16/3481 ,  G11C11/5628 ,  G11C16/08 ,  G11C16/12 ,  G11C16/3459 ,  G11C2211/5621

Abstract: When programming and verifying a memory device which includes a plurality of memory cells and a plurality of word lines, a first coarse programming is first performed on a first memory cell among the plurality of memory cells which is controlled by a first word line among the plurality of word lines, and then a second coarse programming is performed on a second memory cell among the plurality of memory cells which is controlled by a second word line among the plurality of word lines. Next, a first coarse verify current is used for determining whether the first memory cell passes a coarse verification and a second coarse verify current is used for determining whether the second memory cell passes a second coarse verification, wherein the second coarse verify current is smaller than the first coarse verify current.

公开(公告)号：US20180211715A1

公开(公告)日：2018-07-26

申请号：US15810741

申请日：2017-11-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yong-sung CHO ,  Il-han PARK ,  Jung-yun YUN ,  Youn-ho HONG

IPC: G11C16/34 ,  G11C16/04 ,  G11C16/10

CPC classification number: G11C16/3481 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/30 ,  G11C16/3459 ,  G11C2211/5621

Abstract: Provided is a programming method of a nonvolatile memory device, the method comprising the steps of a first programming loop including applying a first verifying voltage to word lines of a plurality of first memory cells for being programmed in a first programming state of a first target threshold voltage and detecting, from among the plurality of first memory cells, a first slow memory cell whose threshold voltage is less than the first verifying voltage, a second programming loop including applying a first program pulse to the first memory cells and applying a second program pulse to the first slow memory cell, a voltage level of the second program pulse of the second program loop being greater than a voltage level of the first program pulse of the second program loop, and a third programming loop.

公开(公告)号：US09941015B2

公开(公告)日：2018-04-10

申请号：US15459170

申请日：2017-03-15

Applicant: TOSHIBA MEMORY CORPORATION

Inventor： Kenichi Abe ,  Masanobu Shirakawa ,  Mizuho Yoshida ,  Takuya Futatsuyama

IPC: G11C16/04 ,  G11C16/34 ,  G11C11/56 ,  G11C16/08

CPC classification number: G11C16/3459 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/16 ,  G11C16/32 ,  G11C16/3445 ,  G11C16/3481 ,  G11C29/42 ,  G11C2211/5621 ,  G11C2211/5648

Abstract: A semiconductor memory device includes first to third pages, first to the third word lines, and a row decoder. In data writing, data is written into the first page before data is written into the second page. The row decoder is configured to apply first to third verify voltages to gates of first to third memory cells in a program verify operation.

公开(公告)号：US20170309329A1

公开(公告)日：2017-10-26

申请号：US15645182

申请日：2017-07-10

Applicant: Kabushiki Kaisha Toshiba ,  SanDisk Technologies LLC

Inventor： Tomoharu Tanaka ,  Jian Chen

IPC: G11C11/56 ,  H01L27/11521 ,  H01L27/115 ,  G11C16/34 ,  G11C16/04 ,  G11C16/12 ,  G11C16/10 ,  H01L27/11524

CPC classification number: G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/12 ,  G11C16/34 ,  G11C16/3418 ,  G11C16/3427 ,  G11C16/3459 ,  G11C16/3481 ,  G11C2211/5621 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524

Abstract: A non-volatile semiconductor memory device includes an electrically data rewritable non-volatile semiconductor memory cell and a write circuit for writing data in the memory cell, the write circuit writing a data in the memory cells by supplying a write voltage Vpgm and a write control voltage VBL to the memory cell, continuing the writing of the data in the memory cell by changing the value of the write control voltage VBL in response to an advent of a first write state of the memory cell and inhibiting any operation of writing a data to the memory cell by further changing the value of the write control voltage VBL to Vdd in response to an advent of a second write state of the memory cell.

公开(公告)号：US09786380B2

公开(公告)日：2017-10-10

申请号：US15233651

申请日：2016-08-10

Applicant: Toshiba Memory Corporation

Inventor： Shinji Suzuki

IPC: G11C16/26 ,  G11C16/34 ,  G11C16/10 ,  G11C16/04 ,  G11C16/08 ,  G11C11/56 ,  G11C16/24

CPC classification number: G11C16/3459 ,  G11C11/5628 ,  G11C16/0466 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24 ,  G11C16/3481 ,  G11C2211/5621

Abstract: A semiconductor memory device includes a memory cell includes a charge storage layer, a word line that is connected to a gate of the memory cell, and a controller that performs a write operation on the memory cell by applying a write voltage to the word line, and a verify operation to verify a threshold voltage of the memory cell after the write operation. The verify operation includes a first verify operation using a first verify voltage, and a second verify operation using a second verify voltage higher than the first verify voltage.

公开(公告)号：US09747990B2

公开(公告)日：2017-08-29

申请号：US15167596

申请日：2016-05-27

Applicant: Renesas Electronics Corporation

Inventor： Masamichi Fujito ,  Hiroshi Yoshida ,  Takanori Takahashi ,  Yasuhiko Taito

IPC: G11C16/20 ,  G11C16/04 ,  G11C16/10 ,  G11C16/34

CPC classification number: G11C16/20 ,  G11C16/0416 ,  G11C16/0425 ,  G11C16/10 ,  G11C16/30 ,  G11C16/32 ,  G11C16/3459 ,  G11C16/3481

Abstract: A semiconductor device includes a memory array having a plurality of complementary cells, each including a first memory element and a second memory element, for holding binary data depending on a difference of threshold voltage therebetween, and a control circuit for initializing the complementary cells. The control circuit performs a first initialization control of reducing the threshold voltage of both the first memory element and the second memory element of the complementary cell and changing the threshold voltage of at least one of the first memory element and the second memory element at an intermediate level lower than a first writing level and higher than an initialization level, a first writing control of changing the threshold voltage of one of the first memory element and the second memory element of the complementary cell at the first writing level, and a second initialization control of changing the threshold voltage of both the first memory element and the second memory element of the complementary cell at the initialization level.

公开(公告)号：US20170069386A1

公开(公告)日：2017-03-09

申请号：US15012440

申请日：2016-02-01

Applicant: SK hynix Inc.

Inventor： Hyun Min SONG ,  Jeong Hoon KIM

IPC: G11C16/10 ,  G11C16/04 ,  G11C16/26

CPC classification number: G11C16/10 ,  G11C16/0408 ,  G11C16/26 ,  G11C16/3459 ,  G11C16/3481

Abstract: A nonvolatile memory device includes a memory cell, and a switching unit. The memory cell includes a cell transistor having a floating gate and a coupling capacitor connected to the floating gate. The switching unit is coupled between the coupling capacitor and a bias terminal, and switches on or off based on the comparison result between a cell current flowing through the memory cell with a reference current during a program operation for programming the memory cell.

Abstract translation: 非易失性存储器件包括存储单元和切换单元。 存储单元包括具有浮置栅极的单元晶体管和连接到浮置栅极的耦合电容器。 开关单元耦合在耦合电容器和偏置端子之间，并且基于在用于对存储器单元进行编程的编程操作期间流过存储器单元的单元电流与参考电流之间的比较结果而导通或截止。