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    ADAPTIVE ERROR AVOIDANCE IN THE MEMORY DEVICES
    1.
    发明公开
    ADAPTIVE ERROR AVOIDANCE IN THE MEMORY DEVICES 审中-公开

    公开(公告)号：US20240363190A1

    公开(公告)日：2024-10-31

    申请号：US18771393

    申请日：2024-07-12

    Applicant: Micron Technology, Inc.

    Inventor： Li-Te Chang ,  Yu-Chung Lien ,  Murong Lang ,  Zhenming Zhou ,  Michael G. Miller

    IPC: G11C29/52 ,  G11C16/08 ,  G11C16/10 ,  G11C16/34

    CPC classification number: G11C29/52 ,  G11C16/08 ,  G11C16/102 ,  G11C16/3404

    Abstract: An example method of performing memory access operations comprises: receiving a request to perform a memory access operation; identifying a block family associated with a set of memory cells; determining, for each logical programming level of a plurality of logical programming levels, a corresponding default block family error avoidance (BFEA) threshold voltage offset value associated with the block family; determining a value of a data state metric associated with the set of memory cells; determining, for each logical programming level of a plurality of logical programming levels, a corresponding sub-BFEA threshold voltage offset value; and performing the memory access operation by applying, for each logical programming level of the plurality of logical programming levels, a combination of the default BFEA threshold voltage value, the sub-BFEA threshold voltage value, and a corresponding base voltage level.

    EVALUATION OF BACKGROUND LEAKAGE TO SELECT WRITE VOLTAGE IN MEMORY DEVICES
    3.
    发明公开
    EVALUATION OF BACKGROUND LEAKAGE TO SELECT WRITE VOLTAGE IN MEMORY DEVICES 审中-公开

    公开(公告)号：US20240331781A1

    公开(公告)日：2024-10-03

    申请号：US18744335

    申请日：2024-06-14

    Applicant: Micron Technology, Inc.

    Inventor： Nevil N. Gajera ,  Karthik Sarpatwari ,  Zhongyuan Lu

    IPC: G11C16/34 ,  G11C16/10 ,  G11C16/26 ,  G11C16/30

    CPC classification number: G11C16/3404 ,  G11C16/10 ,  G11C16/26 ,  G11C16/30 ,  G11C16/3459

    Abstract: Systems, methods, and apparatus related to memory devices. In one approach, a memory device has a memory array including memory cells. A controller of the memory device evaluates background leakage in order to select a write voltage to apply to a memory cell when performing a programming operation. The write voltage is dynamically selected from two or more write voltages. These write voltages include a first write voltage that is a normal or default voltage, and a second write voltage that is a boosted write voltage. The controller applies a pre-sensing voltage and pre-read voltage to the memory cell, and determines first and second respective currents that result from applying these voltages. In response to determining that the first current exceeds a first threshold (indicating background leakage), and the second current is below a second threshold that is greater than the first threshold (indicating that the memory cell does not snap), the controller selects the second (boosted) write voltage.

    MEMORY DEVICE AND METHOD
    4.
    发明公开
    MEMORY DEVICE AND METHOD 审中-公开

    公开(公告)号：US20240321362A1

    公开(公告)日：2024-09-26

    申请号：US18596541

    申请日：2024-03-05

    Applicant: Kioxia Corporation

    Inventor： Hideki IGARASHI ,  Takaya IZUMI

    IPC: G11C16/10 ,  G11C16/04 ,  G11C16/34

    CPC classification number: G11C16/102 ,  G11C16/0433 ,  G11C16/3404

    Abstract: A memory device includes first and second strings including transistors, a first wiring connected to the first string, a second wiring connected to the second string, a third wiring connected to both strings, and a circuit for executing a write operation on a first transistor of the first string and a second transistor of the second string. The operation includes a first operation by which a first voltage is applied to the wirings and a second operation by which a second voltage is applied to gates of the first and second transistors. When a current flows between the first and third wirings but does not flow between the second and third wirings in the first operation, the circuit causes a third voltage to be applied to the first wiring, and causes a fourth voltage higher than the third voltage to be applied to the second wiring in the second operation.

    GENERATION OF QUICK PASS WRITE BIASES IN A MEMORY DEVICE
    7.
    发明公开
    GENERATION OF QUICK PASS WRITE BIASES IN A MEMORY DEVICE 审中-公开

    公开(公告)号：US20240304251A1

    公开(公告)日：2024-09-12

    申请号：US18223358

    申请日：2023-07-18

    Applicant: Western Digital Technologies, Inc.

    Inventor： Abhijith Prakash ,  Xiang Yang

    IPC: G11C16/10 ,  G11C16/08 ,  G11C16/30 ,  G11C16/34

    CPC classification number: G11C16/102 ,  G11C16/08 ,  G11C16/30 ,  G11C16/3404

    Abstract: The memory device includes a quick pass write (QPW) voltage source and a transistor that can control the supply of a first QPW bias voltage to a plurality of bit lines. Control circuitry programs the memory cells of a selected word line in a plurality of program loops. For each memory cell in the selected word line, the control circuitry determines if the memory cell is within either a first or a second QPW zone. If the memory cell is in the second QPW zone, the control circuitry connects the QPW voltage source to the bit line that is in communication with that memory cell to supply the first QPW bias voltage to the bit line. In response to a determination that the memory cell is in the first QPW zone, the control circuitry controls the transistor to supply an average second QPW bias voltage to the bit line.

    TECHNIQUES FOR PARALLEL MEMORY CELL ACCESS
    8.
    发明公开
    TECHNIQUES FOR PARALLEL MEMORY CELL ACCESS 审中-公开

    公开(公告)号：US20240304244A1

    公开(公告)日：2024-09-12

    申请号：US18604192

    申请日：2024-03-13

    Applicant: Micron Technology, Inc.

    Inventor： Paolo Fantini ,  Andrea Martinelli ,  Maurizio Rizzi

    IPC: G11C16/04 ,  G11C16/08 ,  G11C16/24 ,  G11C16/30 ,  G11C16/34

    CPC classification number: G11C16/0433 ,  G11C16/08 ,  G11C16/24 ,  G11C16/30 ,  G11C16/3404

    Abstract: Methods, systems, and devices for techniques for parallel memory cell access are described. A memory device may include multiple tiers of memory cells. During a first duration, a first voltage may be applied to a set of word lines coupled with a tier of memory cells to threshold one or more memory cells included in a first subset of memory cells of the tier. During a second duration, a second voltage may be applied to the set of word lines to write a first logic state to the one or more memory cells of the first subset and to threshold one or more memory cells included in a second subset of memory cells of the tier. During a third duration, a third voltage may be applied to the set of word lines to write a second logic state to the one or more memory cells of the second subset.

    Memory device and operating method using application of pass voltage according to program loops
    9.
    发明授权
    Memory device and operating method using application of pass voltage according to program loops 有权

    公开(公告)号：US12080357B2

    公开(公告)日：2024-09-03

    申请号：US17833114

    申请日：2022-06-06

    Applicant: SK hynix Inc.

    Inventor： Han Soo Joo

    IPC: G11C16/04 ,  G11C16/10 ,  G11C16/34

    CPC classification number: G11C16/3404 ,  G11C16/10

    Abstract: According to an embodiment of the present disclosure, a memory device, a peripheral circuit configured to perform a program operation, including a plurality of program loops, and a control logic configured to, in some of the plurality of loops of the program operation, control the peripheral circuit to apply a program voltage to a selected word line, apply a first pass voltage to adjacent word lines that are adjacent to the selected word line, and then apply a second pass voltage to adjacent word lines at a predetermined time point, wherein the second pass voltage has a different magnitude compared to the first pass voltage, and in the rest of the plurality of loops of the program operation, control the peripheral circuit to apply the second pass voltage to the adjacent word lines at a time point that is different from the predetermined time point from a selected loop.

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