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公开(公告)号：US20240201882A1
公开(公告)日：2024-06-20
申请号：US18220707
申请日：2023-07-11
Applicant: SanDisk Technologies LLC
Inventor： Jiacen Guo , Xiang Yang
IPC: G06F3/06
CPC classification number: G06F3/064 , G06F3/0604 , G06F3/0679
Abstract: The present disclosure is related to a programming technique for a memory device that includes a plurality of memory cells arranged in a plurality of word lines. An operating temperature of the memory device is determined. A spike pre-charge voltage is selected based on the operating temperature of the memory device. A first word line and a second word line are programmed in a first programming pass of a multi-pass programming operation. After the first programming pass is completed on the first and second word lines, the first word line is further programmed in a second programming pass that includes a plurality of program loops with pre-charge operations. The spike pre-charge voltage is applied to the second word line during each pre-charge operation.
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公开(公告)号：US20240194277A1
公开(公告)日：2024-06-13
申请号：US18360306
申请日：2023-07-27
Applicant: SanDisk Technologies LLC
Inventor： Jiacen Guo , Xiang Yang , Yi Song , Jiahui Yuan
CPC classification number: G11C16/3459 , G11C16/08 , G11C16/26
Abstract: Technology is disclosed herein for a memory system that includes control circuits that are configured to connect to a three-dimensional memory structure. The memory structure includes NAND strings arranged in a plurality of rows, a plurality of bit lines connected to the NAND strings and a plurality of word lines, each word line coupled to the plurality of rows of NAND strings. The control circuits are configured to, in a program-verify operation, sense memory cells of a first row of NAND strings coupled to the selected word line for a first sense time and sense memory cells of a second row of NAND strings coupled to the selected word line for a second sense time while applying a program-verify voltage to the selected word line.
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公开(公告)号：US11972820B2
公开(公告)日：2024-04-30
申请号：US17898850
申请日：2022-08-30
Applicant: SanDisk Technologies LLC
Inventor： Jiacen Guo , Dengtao Zhao , Xiang Yang
CPC classification number: G11C16/3459 , G11C16/0433 , G11C16/08 , G11C16/102
Abstract: Memory cells are arranged as NAND strings to form a block divided into sub-blocks, and each NAND string includes a dummy memory cell connected to a dummy word line. Memory cells are programmed by applying programming pulses to a selected word line in a selected sub-block with program-verify performed between pulses. Unselected NAND strings are inhibited from programming by boosting channels of the unselected NAND strings in the selected sub-block from a positive pre-charge voltage to a boosted voltage. The pre-charging of the channels of unselected NAND strings is performed while lowering voltages at the end of program-verify by applying overdrive voltages to data word lines in a sub-block closer to the source line than the selected sub-block and lowering to a resting voltage a dummy word line between the sub-blocks prior to lowering to a resting voltage the data word lines in the sub-block closer to the source line.
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公开(公告)号：US20240029806A1
公开(公告)日：2024-01-25
申请号：US17872148
申请日：2022-07-25
Applicant: SanDisk Technologies LLC
Inventor： Jiacen Guo , Peng Zhang , Xiang Yang , Yanli Zhang
CPC classification number: G11C16/3459 , G11C16/102 , G11C16/08 , G11C16/24 , G11C16/0483
Abstract: In a non-volatile memory system that performs programming of selected memory cells (in coordination with pre-charging and boosting of channels for unselected memory cells) and program-verify to determine whether the programming was successful, the system transitions from program-verify to the next dose of programming by concurrently lowering a voltage applied to a selected word line and voltages applied to word lines on a first side of the selected word line at the conclusion of program-verify. Subsequent to lowering the voltage applied to the selected word line, the system successively lowers voltages applied to groups of one or more word lines on a second side of the selected word line at the conclusion of program-verify beginning with a group of one or more word lines immediately adjacent the selected word line and progressing to other groups of one or more word lines disposed increasingly remote from the selected word line.
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公开(公告)号：US11862260B2
公开(公告)日：2024-01-02
申请号：US17671015
申请日：2022-02-14
Applicant: SanDisk Technologies LLC
Inventor： Jiacen Guo , Swaroop Kaza
CPC classification number: G11C16/349 , G11C16/0483 , G11C16/08 , G11C16/16 , G11C16/3422 , H10B43/27
Abstract: Read disturb audit techniques that include algorithmically applying audit verify voltages to erased wordlines in an open memory block are described. In an audit verify technique, a pass-through voltage ensured to be higher than any threshold voltage of any cell is applied to each wordline in an open memory block that includes one or more programmed memory cells, and an audit verify voltage lower than the pass-through voltage is applied to each erased wordline. A first bit count representing a number of non-conductive bitline(s) is determined and compared to a threshold value to determine whether to continue or discontinue block operation. In an audit verify and audit gap technique, the erased wordlines are divided into disjoint first and second groups, and an audit verify voltage and a non-verify voltage are alternatively applied to the groups in different audit verify stages.
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Patent Agency Ranking
公开(公告)号：US20230386569A1
公开(公告)日：2023-11-30
申请号：US17825193
申请日：2022-05-26
Applicant: SanDisk Technologies LLC
Inventor： Xiang Yang , Muhammad Masuduzzaman , Jiacen Guo
CPC classification number: G11C11/5628 , G11C11/5671 , G11C16/0483 , G11C16/10
Abstract: A method for programming a memory array of a non-volatile memory structure, the memory comprising a population of MLC NAND-type memory cells, wherein the method comprises applying: (1) an inhibit condition to one or more bit lines of the memory array, and (2) a zero voltage condition to one or more bit lines of the memory array such that less than half of the adjacent bit lines of the memory array experience a voltage swing between the inhibit condition and the zero voltage condition.
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公开(公告)号：US20230154550A1
公开(公告)日：2023-05-18
申请号：US17529722
申请日：2021-11-18
Applicant: SanDisk Technologies LLC
Inventor： Jiacen Guo , Xiang Yang , Abhijith Prakash
CPC classification number: G11C16/3445 , G11C16/3404 , G11C16/16 , G11C16/28 , G11C16/08 , G11C16/0433
Abstract: A method of erasing memory cells in a memory device is provided. The method includes grouping a plurality of word lines into a first group, which does not include edge word lines, and a second group, which does include edge word lines. An erase operation is performed on the memory cells of the first and second groups until erase-verify of the memory cells of the first group passes. It is then determined if further erase of the memory cells of the second group is necessary. In response to it being determined that the additional erase operation is necessary, an additional erase operation is performed on at least some of the memory cells of the second group until erase-verify of the memory cells of the second group passes.
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公开(公告)号：US12142315B2
公开(公告)日：2024-11-12
申请号：US17825193
申请日：2022-05-26
Applicant: SanDisk Technologies LLC
Inventor： Xiang Yang , Muhammad Masuduzzaman , Jiacen Guo
Abstract: A method for programming a memory array of a non-volatile memory structure, the memory comprising a population of MLC NAND-type memory cells, wherein the method comprises applying: (1) an inhibit condition to one or more bit lines of the memory array, and (2) a zero voltage condition to one or more bit lines of the memory array such that less than half of the adjacent bit lines of the memory array experience a voltage swing between the inhibit condition and the zero voltage condition.
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公开(公告)号：US20240145006A1
公开(公告)日：2024-05-02
申请号：US18357467
申请日：2023-07-24
Applicant: SanDisk Technologies LLC
Inventor： Peng Zhang , Yanli Zhang , Dengtao Zhao , Jiacen Guo
CPC classification number: G11C16/08 , G11C16/0483 , G11C16/10 , G11C16/3459 , H01L25/0657
Abstract: Memory cells of a second sub-block are programmed by pre-charging channels of unselected memory cells connected to the selected word line, boosting the pre-charged channels of unselected memory cells and applying a program voltage to selected non-volatile memory cells connected to the selected word line. The pre-charging includes applying one or more overdrive voltages to word lines connected to memory cells of a first sub-block to provide a conductive path from memory cells of the second sub-block through the first sub-block to a source line and maintaining the word lines connected to memory cells of the first sub-block at one or more overdrive voltages while ramping down signals at the end of the pre-charging. Dummy word lines, positioned between sub-blocks, are maintained at a resting voltage during the boosting in order to cut-off channels of memory cells in the second sub-block from channels of memory cells in the first sub-block.
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公开(公告)号：US11972813B2
公开(公告)日：2024-04-30
申请号：US17556477
申请日：2021-12-20
Applicant: SanDisk Technologies LLC
Inventor： Jiacen Guo , Xiang Yang , Swaroop Kaza , Laidong Wang
CPC classification number: G11C16/3459 , G11C16/102 , G11C16/26 , G11C16/32 , G11C16/3409
Abstract: A memory device with adaptive sense time tables is disclosed. In order to maintain a desired (initial or preset) threshold voltage distribution, the sense time is adjusted as the program-erase cycle count increases. The program-erase cycle process tends to wear down memory cells, causing the QPW window to expand and the threshold voltage to widen. However, by adjusting (i.e., reducing) the sense time for increased program-erase cycles, the QPW window and the threshold voltage can be at least substantially maintained. Additionally, systems and methods for adjusting sense time based on die-to-die variations are also disclosed.
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