公开(公告)号：US12087363B2

公开(公告)日：2024-09-10

申请号：US18109466

申请日：2023-02-14

Applicant: SanDisk Technologies LLC

Inventor： Abhijith Prakash ,  Anubhav Khandelwal

IPC: G11C11/00 ,  G11C11/18 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/32 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10 ,  H10B43/27

CPC classification number: G11C16/08 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/32 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10 ,  H10B43/27

Abstract: The nonvolatile memory includes a plurality of nonvolatile memory cells configured to store multiple data states; a word line connected to a control gate of at least one of the plurality of non-volatile memory cells; a control gate line to supply a control gate signal; a word line switch connected between the word line and the control gate line to control the potential applied to the word line from the control gate line; and a memory controller circuit. The memory controller circuit is configured to control a word line potential on the word line and a control gate potential on the control gate line and to control a state of the control gate. The memory controller circuit, when the nonvolatile memory transitions to a not-on state, is further configured to turn off the word line switch and to charge the control gate line to a charged potential.

公开(公告)号：US20240212767A1

公开(公告)日：2024-06-27

申请号：US18225248

申请日：2023-07-24

Applicant: SanDisk Technologies LLC

Inventor： Abhijith Prakash ,  Xiang Yang

IPC: G11C16/34 ,  G11C16/08 ,  G11C16/10

CPC classification number: G11C16/3459 ,  G11C16/08 ,  G11C16/102

Abstract: The memory device includes a memory block with an array of memory cells arranged word lines. The memory device also includes control circuitry that is configured to program final data into a selected word line in a multi-pass programming operation that includes a first pass and a second pass. In the first pass, the control circuitry is configured to program the memory cells of the selected word line to foggy data and program parity data in the memory device. The parity data includes three possible data states. Prior to the second pass, the control circuitry is configured to read the foggy data and the parity data and reconstruct the final data from the foggy data and the parity data. In the second pass, the control circuitry is configured to program the memory cells of the selected word line from the foggy data to the final data.

公开(公告)号：US11972818B2

公开(公告)日：2024-04-30

申请号：US17841343

申请日：2022-06-15

Applicant: SanDisk Technologies LLC

Inventor： Abhijith Prakash ,  Xiang Yang

IPC: G11C16/34 ,  G11C11/56 ,  G11C16/10 ,  G11C16/26

CPC classification number: G11C16/3459 ,  G11C11/5628 ,  G11C11/5642 ,  G11C11/5671 ,  G11C16/10 ,  G11C16/26

Abstract: A memory apparatus and method of operation are provided. The apparatus includes memory cells each connected to word lines. The memory cells are disposed in strings and configured to retain a threshold voltage corresponding to data states. A control means is configured to apply verification pulses of program verify voltages each associated with one of the data states to selected ones of the word lines to determine whether the memory cells connected thereto have the threshold voltage above each of the program verify voltages targeted for each of the memory cells during a program-verify portion of a program operation. The control means is also configured to trim the program verify voltages for each of the data states for a grouping of the memory cells based on quantities of the memory cells having the threshold voltage crossing over between the data states in crossovers in a verify level trimming process.

公开(公告)号：US20230343400A1

公开(公告)日：2023-10-26

申请号：US17724769

申请日：2022-04-20

Applicant: SanDisk Technologies LLC

Inventor： Jiacen Guo ,  Xiang Yang ,  Abhijith Prakash

IPC: G11C16/34 ,  G11C11/56 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10

CPC classification number: G11C16/3427 ,  G11C11/5671 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/3459

Abstract: A memory apparatus and method of operation are provided. The apparatus includes memory cells connected to word lines and disposed in strings. A control means is coupled to the word lines and the strings and is configured to ramp a voltage applied to a selected one of the word lines from a verify voltage to a reduced voltage during a program-verify portion of a program operation. The control means successively ramps voltages applied to each of a plurality of neighboring ones of the word lines from a read pass voltage to the reduced voltage beginning with ones of the plurality of neighboring ones of the word lines immediately adjacent the selected one of the word lines and progressing to ones of the plurality of neighboring others of the word lines disposed increasingly remotely from the selected one of the word lines during the program-verify portion of the program operation.

公开(公告)号：US20220415416A1

公开(公告)日：2022-12-29

申请号：US17355684

申请日：2021-06-23

Applicant: SanDisk Technologies LLC

Inventor： Abhijith Prakash ,  Xiang Yang

IPC: G11C16/34 ,  G11C16/14 ,  G11C16/10 ,  G11C16/26

Abstract: Non-volatile memory systems are disclosed. The memory systems include rows of memory holes FC-SGD and SC-SGD, the latter of which may be created by a SHE cutting operation. The SC-SGD include erase speeds slower than those of FC-SGD. In order to overcome the erase speed disparities, SC-SGD are programmed to a higher Vt as compared to FC-SGD. By programming SC-SGD to a higher Vt, the erase speed increases and matches the erase speed of FC-SGD. Further, different SC-SGDs are cut to different amounts, creating different erase speeds among SC-SGD. SC-SGDs with a greater degree/amount of cut have slower erase speeds as compared to SC-SGDs with a lesser degree/amount of cut. However, verify levels among SC-SGDs can differ to produce SC-SGDs with Vt's such that their erase speeds match with each other as well as with FC-SGD.

公开(公告)号：US20220284961A1

公开(公告)日：2022-09-08

申请号：US17191474

申请日：2021-03-03

Applicant: SanDisk Technologies LLC

Inventor： Abhijith Prakash ,  Anubhav Khandelwal

IPC: G11C16/08 ,  G11C16/04 ,  G11C16/32 ,  G11C16/10

Abstract: The nonvolatile memory includes a plurality of nonvolatile memory cells configured to store multiple data states; a word line connected to a control gate of at least one of the plurality of non-volatile memory cells; a control gate line to supply a control gate signal; a word line switch connected between the word line and the control gate line to control the potential applied to the word line from the control gate line; and a memory controller circuit. The memory controller circuit is configured to control a word line potential on the word line and a control gate potential on the control gate line and to control a state of the control gate. The memory controller circuit, when the nonvolatile memory transitions to a not-on state, is further configured to turn off the word line switch and to charge the control gate line to a charged potential.

公开(公告)号：US20210257039A1

公开(公告)日：2021-08-19

申请号：US16790362

申请日：2020-02-13

Applicant: SanDisk Technologies LLC

Inventor： Abhijith Prakash ,  Jiahui Yuan

IPC: G11C16/34 ,  G11C16/04 ,  G11C11/56 ,  G11C5/14

Abstract: Apparatuses and techniques are described for periodically refreshing word line voltages in a block of memory cells based on the susceptibility of the block to read errors. One source of read errors is delayed read disturb which results from a low word line voltage during idle periods of the memory device. In one aspect, periodic refresh operations are optimized based on factors such as a number of bits per cell in the block and number of program-erase (P-E) cycles. For example, at high P-E cycles, the amplitude of a refresh voltage for a single-level cell (SLC) block can be 0 V or lower while the amplitude of a refresh voltage for a multi-level cell (MLC) block can be an intermediate voltage between 0 V and a pass voltage.

公开(公告)号：US11961573B2

公开(公告)日：2024-04-16

申请号：US17533292

申请日：2021-11-23

Applicant: SanDisk Technologies LLC

Inventor： Abhijith Prakash ,  Xiang Yang ,  Dengtao Zhao

IPC: G11C16/06 ,  G11C16/04 ,  G11C16/10 ,  G11C16/26 ,  G11C16/34

CPC classification number: G11C16/3459 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/26

Abstract: A plurality of memory programming the memory cells to at least one programmed data state in a plurality of program-verify iterations. In each iteration, after a programming pulse, a sensing operation is conducted to compare the threshold voltages of the memory cells to a low verify voltage associated with a first programmed data state and to a high very voltage associated with the first programmed data state. The sensing operation includes discharging a sense node through a bit line coupled to one of the memory cells and monitoring a discharge time of the sense node. At least one aspect of the sensing operation is temperature dependent so that a voltage gap between the high and low verify voltages is generally constant across a range of temperatures.

公开(公告)号：US11894067B2

公开(公告)日：2024-02-06

申请号：US17551640

申请日：2021-12-15

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Abhijith Prakash ,  Shubhajit Mukherjee

IPC: G06F12/00 ,  G11C16/26 ,  G11C16/04 ,  G11C16/34 ,  G11C16/32 ,  G11C16/16

CPC classification number: G11C16/26 ,  G06F12/00 ,  G11C16/0483 ,  G11C16/16 ,  G11C16/32 ,  G11C16/3404

Abstract: A memory apparatus and method of operation are provided. The memory apparatus includes memory cells configured to retain a threshold voltage. The memory cells are connected to one of a plurality of word lines and are arranged in strings comprising a plurality of blocks. A control means is coupled to the plurality of word lines and the strings and is configured to periodically determine a read frequency metric associated with a plurality of read operations of one of the plurality of blocks of the memory cells. The control means is also configured to relocate data of the one of the plurality of blocks and cause the one of the plurality of blocks to remain unused for a predetermined relaxation time based on the read frequency metric.

公开(公告)号：US20230410901A1

公开(公告)日：2023-12-21

申请号：US17752524

申请日：2022-05-24

Applicant: SanDisk Technologies LLC

Inventor： Dong-Il Moon ,  Abhijith Prakash ,  Wei Zhao ,  Henry Chin

IPC: G11C11/56 ,  G11C16/26

CPC classification number: G11C11/5642 ,  G11C16/26 ,  G11C11/5671

Abstract: A memory apparatus and method of operation are provided. The apparatus includes memory cells each connected to one of a plurality of word lines. The memory cells are disposed in strings and configured to retain a threshold voltage corresponding to one of a plurality of data states. A control means is coupled to the plurality of word lines and the strings and is configured to apply a read voltage to a selected ones of the plurality of word lines during a read operation and ramp down to a discharge voltage at an end of the read operation and apply a ready voltage to the selected ones of the plurality of word lines during a ready period of time following the read operation. The control means is also configured to adjust at least one of the discharge voltage and the ready voltage based on a temperature of the memory apparatus.