公开(公告)号：US12224014B2

公开(公告)日：2025-02-11

申请号：US17864609

申请日：2022-07-14

Applicant: Western Digital Technologies, Inc.

Inventor： Harish Gajula ,  Bhanushankar Doni

IPC: G11C16/16 ,  G11C16/10 ,  G11C16/26

Abstract: Technology is disclosed herein for multi-stage data compaction. In a first data compaction stage valid data fragments from source erase block(s) are programmed into a destination erase block at two bits per memory cell. In a second data compaction stage additional valid data from the source erase block(s) is programmed into the destination erase block at two bits per memory cell. In this second stage, the same physical pages of memory cells in the destination erase block may be programmed such that each memory cell in the destination erase block is programmed to four bits.

公开(公告)号：US12211558B2

公开(公告)日：2025-01-28

申请号：US18177730

申请日：2023-03-02

Applicant: Kioxia Corporation

Inventor： Yasuhiro Uchimura

IPC: G11C16/30 ,  G11C16/04 ,  G11C16/16 ,  G11C16/34 ,  H10B41/27 ,  H10B43/27

Abstract: According to one embodiment, in a semiconductor storage device, during an erasing operation, a voltage supplied to at least one of a first wiring and a second wiring is set as a first voltage, and a voltage supplied to a first conductive layer is set as a second voltage. The erasing operation includes a first operation period in which the first voltage is increased from a first reference voltage to a first erase voltage and the second voltage is increased from a second reference voltage to a second erase voltage. In a second operation period of the erasing operation, the first voltage is maintained at the first erase voltage and the second voltage is decreased from the second erase voltage to the second reference voltage (or a first level voltage larger than the second reference voltage) after the first operation period.

公开(公告)号：US12205649B2

公开(公告)日：2025-01-21

申请号：US17950931

申请日：2022-09-22

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Tao Yang ,  Dongxue Zhao ,  Lei Liu ,  Kun Zhang ,  Wenxi Zhou ,  Zhiliang Xia ,  Zongliang Huo

IPC: G11C16/16 ,  G11C16/04

Abstract: A method for data erasing of a non-volatile memory device is disclosed. The memory includes multiple memory cell strings each including a select gate transistor and multiple memory cells that are connected in series. The method comprises applying a step erase voltage to one memory cell string for an erase operation, the step erase voltage having a step-rising shaped voltage waveform. The method further comprises, during a period when the step erase voltage rises from an intermediate level to a peak level, raising a voltage of the select gate transistor from a starting level to a peak level, and raising a voltage of a predetermined region from a starting level to a peak level, such that a gate-induced drain leakage current is generated in the one memory cell string. The predetermined region is adjacent to the at least one select gate transistor and includes at least one memory cell.

公开(公告)号：US12198769B2

公开(公告)日：2025-01-14

申请号：US17741074

申请日：2022-05-10

Applicant: SanDisk Technologies LLC

Inventor： Huiwen Xu ,  Bo Lei ,  Jun Wan

IPC: G11C11/00 ,  G11C16/08 ,  G11C16/16 ,  G11C16/26 ,  G11C16/34

Abstract: An apparatus disclosed herein comprises: a plurality of memory cells and a control circuit coupled to the plurality of memory cells. The control circuit is configured to: erase a block; verify, using a first erase verify level, that the block was properly erased; verify, using a second erase verify level, that the block was properly erased; determine whether there are any mismatches in a plurality of verify statuses between neighboring wordlines of the block from verifying the block using the second erase verify level; and identify, based on the determination, whether the block has failed.

公开(公告)号：US20250014658A1

公开(公告)日：2025-01-09

申请号：US18598988

申请日：2024-03-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Youhwan Kim ,  Kyungduk Lee ,  Suyong Jang ,  Hankyu Ko ,  Ho-Sung Ahn

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/16 ,  G11C16/28

Abstract: The present disclosure relates to storage devices. An example storage device includes a nonvolatile memory device that includes a plurality of memory blocks, and a memory controller that controls the nonvolatile memory device. The memory controller performs a soft erase operation on a first memory block among the plurality of memory blocks, measures a first cell count by applying a first reference voltage to a plurality of first memory cells selected in advance from a plurality of memory cells of the first memory block after performing the soft erase operation, generates a first health index associated with a retention characteristic of the first memory block based on the first cell count, and performs a reliability management operation on the first memory block based on the first health index.

公开(公告)号：US20250014651A1

公开(公告)日：2025-01-09

申请号：US18540068

申请日：2023-12-14

Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

Inventor： Li Xiang ,  Wei Huang ,  Ting Zhu ,  Shuai Wang

IPC: G11C16/16 ,  G11C16/04 ,  G11C16/08

Abstract: According to one aspect of the present disclosure, a method of operating a memory is provided. The method may include applying a bias voltage to a bottom select line of a second memory block of the memory during a first time period to turn on the bottom select transistor of the second memory block. The memory may include a first memory block and the second memory block, and the bottom select transistor is coupled to a bottom select line. The method may include performing a first erase operation during a second time period after the first time period by providing an erase operating voltage to a source line of the first memory block, and setting the bottom select line of the second memory block to a floating state.

公开(公告)号：US12190961B2

公开(公告)日：2025-01-07

申请号：US17988090

申请日：2022-11-16

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Giovanni Maria Paolucci ,  Paolo Tessariol ,  Emilio Camerlenghi ,  Gianpietro Carnevale ,  Augusto Benvenuti

IPC: G11C16/16 ,  G11C16/04 ,  G11C16/24 ,  G11C16/30

Abstract: Methods of operating a memory, and memory configured to perform similar methods, might include applying a negative first voltage level to a control gate of a transistor connected between a first node and a string of series-connected memory cells, increasing a voltage level applied to the first node at a particular rate while increasing the voltage level applied to the control gate of the transistor at the particular rate, and in response to the voltage level applied to the first node reaching a particular voltage level, ceasing increasing the voltage level applied to the first node and ceasing increasing the voltage level applied to the control gate of the transistor.

公开(公告)号：US12190960B2

公开(公告)日：2025-01-07

申请号：US17976566

申请日：2022-10-28

Applicant: Kioxia Corporation

Inventor： Kengo Kurose ,  Masanobu Shirakawa ,  Hideki Yamada ,  Marie Takada

IPC: G11C16/04 ,  G06F3/06 ,  G11C11/56 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  G11C16/34 ,  H10B41/27 ,  H10B43/27

Abstract: According to one embodiment, a memory system includes a semiconductor memory device and a controller. The semiconductor memory device includes a first memory cell configured to store data. The controller is configured to output a first parameter and a first command. The first parameter relates to an erase voltage for a first erase operation with respect to the first memory cell. The first command instructs the first erase operation. The controller outputs the first command after outputting the first parameter to the semiconductor memory device.

公开(公告)号：US12190953B2

公开(公告)日：2025-01-07

申请号：US17541103

申请日：2021-12-02

Applicant: KIOXIA CORPORATION

Inventor： Xu Li

IPC: G11C16/24 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/16 ,  G11C16/30 ,  G11C16/32 ,  G11C16/34 ,  H10B69/00

Abstract: A semiconductor memory device includes a memory cell array, a well voltage control circuit, and a source voltage control circuit. Before writing data, first and second transistors respectively connected to a select gate line and a word line are turned on at a first timing, and a ground voltage is applied to the first transistor at a second timing and to the second transistor at a third timing. The source voltage control circuit applies a first voltage to the source line at a fourth timing that is simultaneous with or after the first timing and before the second timing, and the well voltage control circuit applies the first voltage to the well region at a fifth timing that is simultaneous with or after the first timing and before the second timing, and applies a ground voltage to the well region at a sixth timing that is after the fifth timing.

公开(公告)号：US12183402B2

公开(公告)日：2024-12-31

申请号：US18063912

申请日：2022-12-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jun-Ho Seo ,  Yong-Wan Son ,  Dogyeong Lee ,  Youngha Choi

IPC: G11C16/04 ,  G11C16/10 ,  G11C16/16 ,  G11C16/34

Abstract: Disclosed is an operation method of a memory device that includes a memory block including a plurality of cell transistors stacked in a direction perpendicular to a substrate. The plurality of cell transistors may include a ground selection transistor and an erase control transistor. The erase control transistor may be between the substrate and the ground selection transistor. The operation method may include performing a first erase operation on the ground selection transistor, performing a first program operation on the erase control transistor after the first erase operation, performing a second program operation on the ground selection transistor after the first program operation, and performing a second erase operation on the erase control transistor after the second program operation.