公开(公告)号：US11715536B2

公开(公告)日：2023-08-01

申请号：US17536270

申请日：2021-11-29

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Daniele Cantarelli ,  Augusto Benvenuti ,  Massimo Ernesto Bertuccio

IPC: G11C16/04 ,  G11C16/24 ,  G11C16/26 ,  G11C16/34 ,  G11C16/10 ,  G11C11/56 ,  G11C16/32 ,  G11C7/12

CPC classification number: G11C16/3459 ,  G11C11/5628 ,  G11C11/5642 ,  G11C11/5671 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/26 ,  G11C16/32 ,  G11C16/3427 ,  G11C7/12 ,  G11C16/04 ,  G11C2211/5621

Abstract: Apparatus might include an array of memory cells comprising a plurality of strings of series-connected memory cells and a controller for access of the array of memory cells, wherein the controller is configured to cause the apparatus to perform a sense operation on a selected memory cell of a string of series-connected memory cells, and to discharge access lines connected to the string of series-connected memory cells in a defined manner following the sense operation.

公开(公告)号：US20230075673A1

公开(公告)日：2023-03-09

申请号：US17987779

申请日：2022-11-15

Applicant: Micron Technology, Inc.

Inventor： Ramanathan Gandhi ,  Augusto Benvenuti ,  Giovanni Maria Paolucci

IPC: H01L29/51

Abstract: A transistor comprises a channel region having a frontside and a backside. A gate is adjacent the frontside of the channel region with a gate insulator being between the gate and the channel region. Insulating material having net negative charge is adjacent the backside of the channel region. The insulating material comprises at least one of AlxFy, HfAlxFy, AlOxNy, and HfAlxOyNz, where “x”, “y”, and “z” are each greater than zero. Other embodiments and aspects are disclosed.

公开(公告)号：US11417396B2

公开(公告)日：2022-08-16

申请号：US17067550

申请日：2020-10-09

Applicant: Micron Technology, Inc.

Inventor： Albert Fayrushin ,  Augusto Benvenuti ,  Akira Goda ,  Luca Laurin ,  Haitao Liu

IPC: G11C16/08 ,  G11C16/24 ,  G11C16/04 ,  G11C16/16 ,  G11C16/26

Abstract: Some embodiments include apparatuses and methods of operating the apparatuses. One of the apparatuses includes a memory cell string having first, second, third, fourth, and fifth memory cells; access lines including first, second, third, fourth, and fifth access lines coupled to the first, second, third, fourth, and fifth memory cells, respectively, and a module. The first memory cell is between the second and third memory cells. The second memory cell is between the first and fourth memory cells. The third memory cell is between the first and fifth memory cells. The module is to couple the first access line to a ground node at a first time of a memory operation, couple the second and third access lines to the ground node at a second time of the operation after the first time, and couple the fourth and fifth access lines to the ground node at a third time of the operation after the second time.

公开(公告)号：US20140085973A1

公开(公告)日：2014-03-27

申请号：US13624627

申请日：2012-09-21

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Fabio Pellizzer ,  Antonino Rigano ,  Marcello Mariani ,  Augusto Benvenuti

IPC: H01L21/768 ,  H01L27/24 ,  G11C11/00 ,  H01L21/762

CPC classification number: H01L27/2445 ,  G11C13/0004 ,  H01L21/3086 ,  H01L21/762 ,  H01L27/2463 ,  H01L29/42304 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/16 ,  H01L45/1675

Abstract: Embodiments disclosed herein may relate to forming a contact region for an interconnect between a selector transistor and a word-line electrode in a memory device.

Abstract translation: 本文公开的实施例可以涉及在存储器件中形成用于选择器晶体管和字线电极之间的互连的接触区域。

公开(公告)号：US20220392533A1

公开(公告)日：2022-12-08

申请号：US17888041

申请日：2022-08-15

Applicant: Micron Technology, Inc.

Inventor： Albert Fayrushin ,  Augusto Benvenuti ,  Akira Goda ,  Luca Laurin ,  Haitao Liu

IPC: G11C16/08 ,  G11C16/24 ,  G11C16/04 ,  G11C16/16 ,  G11C16/26

Abstract: Some embodiments include apparatuses and methods of operating the apparatuses. One of the apparatuses includes a memory cell string having first, second, third, fourth, and fifth memory cells; access lines including first, second, third, fourth, and fifth access lines coupled to the first, second, third, fourth, and fifth memory cells, respectively, and a module. The first memory cell is between the second and third memory cells. The second memory cell is between the first and fourth memory cells. The third memory cell is between the first and fifth memory cells. The module is to couple the first access line to a ground node at a first time of a memory operation, couple the second and third access lines to the ground node at a second time of the operation after the first time, and couple the fourth and fifth access lines to the ground node at a third time of the operation after the second time.

公开(公告)号：US20220271127A1

公开(公告)日：2022-08-25

申请号：US17182737

申请日：2021-02-23

Applicant: Micron Technology, Inc.

Inventor： Ramanathan Gandhi ,  Augusto Benvenuti ,  Giovanni Maria Paolucci

IPC: H01L29/10 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/788 ,  H01L29/792

Abstract: A transistor comprises a channel region having a frontside and a backside. The channel region comprises a frontside channel material at the frontside and a backside channel material at the backside. A gate is adjacent the frontside of the channel region, with a gate insulator being between the gate and the channel region. The frontside channel material has total n-type dopant therein of greater than 1×1018 atoms/cm3 to no greater than 1×1020 atoms/cm3. The backside channel material has total n-type dopant therein of 0 atoms/cm3 to 1×1018 atoms/cm3. Other embodiments and aspects are disclosed.

公开(公告)号：US11200958B2

公开(公告)日：2021-12-14

申请号：US17091379

申请日：2020-11-06

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Daniele Cantarelli ,  Augusto Benvenuti ,  Massimo Ernesto Bertuccio

IPC: G11C16/04 ,  G11C16/26 ,  G11C16/24 ,  G11C16/34 ,  G11C16/10 ,  G11C11/56 ,  G11C16/32 ,  G11C7/12

Abstract: Memories might include an array of memory cells comprising a plurality of strings of series-connected memory cells and a controller for access of the array of memory cells, wherein the controller is configured to perform a sense operation on a particular memory cell of a string of series-connected memory cells, discharge the access line for a second memory cell of the string of series-connected memory cells to a first voltage level and discharge the access line for the particular memory cell to a second voltage level higher than the first voltage level after completion of the sense operation, and discharge the access line for a third memory cell of the string of series-connected memory cells to a third voltage level lower than the second voltage level and higher than the first voltage level after initiating the discharge of the access line for the particular memory cell.

公开(公告)号：US20210233591A1

公开(公告)日：2021-07-29

申请号：US17228807

申请日：2021-04-13

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Giovanni Maria Paolucci ,  Paolo Tessariol ,  Emilio Camerlenghi ,  Gianpietro Carnevale ,  Augusto Benvenuti

IPC: G11C16/16 ,  G11C16/04 ,  G11C16/24 ,  G11C16/30

Abstract: Methods of operating a memory, and memory configured to perform similar methods, might include applying a positive first voltage level to a first node selectively connected to a string of series-connected memory cells while applying a negative second voltage level to a control gate of a transistor connected between the first node and the string of series-connected memory cells, and increasing the voltage level applied to the first node to a third voltage level while increasing the voltage level applied to the control gate of the transistor to a fourth voltage level lower than the third voltage level and higher than the first voltage level.

公开(公告)号：US20210065827A1

公开(公告)日：2021-03-04

申请号：US17091379

申请日：2020-11-06

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Daniele Cantarelli ,  Augusto Benvenuti ,  Massimo Ernesto Bertuccio

IPC: G11C16/34 ,  G11C16/26 ,  G11C16/04 ,  G11C16/10 ,  G11C11/56 ,  G11C16/32

Abstract: Memories might include an array of memory cells comprising a plurality of strings of series-connected memory cells and a controller for access of the array of memory cells, wherein the controller is configured to perform a sense operation on a particular memory cell of a string of series-connected memory cells, discharge the access line for a second memory cell of the string of series-connected memory cells to a first voltage level and discharge the access line for the particular memory cell to a second voltage level higher than the first voltage level after completion of the sense operation, and discharge the access line for a third memory cell of the string of series-connected memory cells to a third voltage level lower than the second voltage level and higher than the first voltage level after initiating the discharge of the access line for the particular memory cell.

公开(公告)号：US20240069749A1

公开(公告)日：2024-02-29

申请号：US18236087

申请日：2023-08-21

Applicant: Micron Technology, Inc.

Inventor： Augusto Benvenuti ,  Giovanni Maria Paolucci ,  Alessio Urbani ,  Gianpietro Carnevale ,  Aurelio Giancarlo Mauri

IPC: G06F3/06

CPC classification number: G06F3/0619 ,  G06F3/0655 ,  G06F3/0679

Abstract: A memory access operation is initiated to read a set of target memory cells of a target wordline of the memory device. During the memory access operation, a read voltage level is caused to be applied to the target wordline. During the memory access operation, a first pass through voltage level is caused to be applied to a first wordline adjacent to the target wordline. During the memory access operation, a second pass through voltage is caused to be applied to a second wordline adjacent to the target wordline, wherein the first pass through voltage level is less than the second pass through voltage level.