公开(公告)号：US12178054B2

公开(公告)日：2024-12-24

申请号：US17677577

申请日：2022-02-22

Applicant: Micron Technology, Inc.

Inventor： Paolo Fantini ,  Fabio Pellizzer ,  Lorenzo Fratin

IPC: H10B63/00 ,  G11C13/00 ,  H10B20/00 ,  H10N70/00

Abstract: Methods, systems, and devices for split pillar architectures for memory devices are described. A memory device may include a substrate arranged with conductive contacts in a pattern and openings through alternative layers of conductive and insulative material that may decrease the spacing between the openings while maintaining a dielectric thickness to sustain the voltage to be applied to the array. After etching material, an insulative material may be deposited in a trench. Portions of the insulative material may be removed to form openings, into which cell material is deposited. Conductive pillars may extend perpendicular to the planes of the conductive material and the substrate, and couple to conductive contacts. The conductive pillars may be divided to form first and second pillars.

公开(公告)号：US20240284660A1

公开(公告)日：2024-08-22

申请号：US18441942

申请日：2024-02-14

Applicant: Micron Technology, Inc.

Inventor： Lorenzo Fratin ,  Paolo Fantini ,  Enrico Varesi ,  Fabio Pellizzer

IPC: H10B12/00 ,  G11C5/06 ,  G11C5/10 ,  G11C11/408

CPC classification number: H10B12/485 ,  G11C5/063 ,  G11C5/10 ,  G11C11/4085 ,  H10B12/03 ,  H10B12/482 ,  H10B12/488

Abstract: Methods, systems, and devices for split pillar and pier memory architectures are described. A memory array may include a first set of word line plates separated from a second set of word line plates by a trench and a set of pairs of pillars (e.g., that are configured as digit lines) that interact with the first and second set of word line plates. Further, the memory array may include a set of dielectric piers that are positioned between the pairs of pillars, where each dielectric pier contacts a first pillar from a first pair and a second pillar from a second pair. Additionally, the memory array may include a set of storage elements that are each coupled with a word line plate, a pillar, and a dielectric material that is positioned between each first and second pillar of the pairs of pillars.

公开(公告)号：US11894103B2

公开(公告)日：2024-02-06

申请号：US17231661

申请日：2021-04-15

Applicant: Micron Technology, Inc.

Inventor： Paolo Fantini ,  Lorenzo Fratin ,  Fabio Pellizzer ,  Enrico Varesi

IPC: G11C8/14 ,  G11C8/08 ,  G11C8/10 ,  G11C5/14 ,  G11C5/06

CPC classification number: G11C8/08 ,  G11C5/06 ,  G11C5/14 ,  G11C8/10 ,  G11C8/14

Abstract: Methods, systems, and devices for a decoding architecture for memory devices are described. Word line plates of a memory array may each include a sheet of conductive material that includes a first portion extending in a first direction within a plane along with multiple fingers extending in a second direction within the plane. Memory cells coupled with a word line plate, or a subset thereof, may represent a logical page for accessing memory cells. Each word line plate may be coupled with a corresponding word line driver via a respective electrode. A memory cell may be accessed via a first voltage applied to a word line plate coupled with the memory cell and a second voltage applied to a pillar electrode coupled with the memory cell. Parallel or simultaneous access operations may be performed for two or more memory cells within a same page of memory cells.

公开(公告)号：US11887661B2

公开(公告)日：2024-01-30

申请号：US17647578

申请日：2022-01-10

Applicant: Micron Technology, Inc.

Inventor： Innocenzo Tortorelli ,  Fabio Pellizzer ,  Mattia Robustelli ,  Alessandro Sebastiani

IPC: G11C13/00

CPC classification number: G11C13/003 ,  G11C13/0004 ,  G11C13/004 ,  G11C13/0023 ,  G11C13/0069 ,  G11C2213/71

Abstract: Methods, systems, and devices for a cross-point pillar architecture for memory arrays are described. Multiple selector devices may be configured to access or activate a pillar within a memory array, where the selector devices may each be or include a chalcogenide material. A pillar access line may be coupled with multiple selector devices, where each selector device may correspond to a pillar associated with the pillar access line. Pillar access lines on top and bottom of the pillars of the memory array may be aligned in a square or rectangle formation, or in a hexagonal formation. Pillars and corresponding selector devices on top and bottom of the pillars may be located at overlapping portions of the pillar access lines, thereby forming a cross point architecture for pillar selection or activation. The selector devices may act in pairs to select or activate a pillar upon application of a respective selection voltage.

公开(公告)号：US20230329010A1

公开(公告)日：2023-10-12

申请号：US17714771

申请日：2022-04-06

Applicant: Micron Technology, Inc.

Inventor： Fabio Pellizzer ,  Russell L. Meyer ,  Stephen W. Russell ,  Lorenzo Fratin

IPC: H01L27/24 ,  H01L45/00

CPC classification number: H01L27/249 ,  H01L45/06 ,  H01L45/141 ,  H01L45/1675

Abstract: Methods, systems, and devices for trench and pier architectures for three-dimensional memory arrays are described. A semiconductor device (e.g., a memory die) may include pier structures formed in contact with features formed from alternating layers of materials deposited over a substrate, which may provide support for subsequent processing. For example, a memory die may include alternating layers of a first material and a second material, which may be formed into various cross-sectional patterns. Pier structures may be formed in contact with the cross sectional patterns such that, when either the first material or the second material is removed to form voids, the pier structures may provide mechanical support of the cross-sectional pattern of the remaining material. In some examples, such pier structures may be formed within or along trenches or other features aligned along a direction of a memory array, which may provide a degree of self-alignment for subsequent operations.

公开(公告)号：US11764146B2

公开(公告)日：2023-09-19

申请号：US17379257

申请日：2021-07-19

Applicant: Micron Technology, Inc.

Inventor： Stephen W. Russell ,  Fabio Pellizzer ,  Lorenzo Fratin

IPC: H01L21/00 ,  H01L23/522 ,  H01L21/768

CPC classification number: H01L23/5226 ,  H01L21/76846 ,  H01L21/76871 ,  H01L21/76877

Abstract: Methods for forming microelectronic device structures include forming interconnects that are self-aligned with both a lower conductive structure and an upper conductive structure. At least one lateral dimension of an interconnect is defined upon subtractively patterning the lower conductive structure along with a first sacrificial material. At least one other lateral dimension of the interconnect is defined by patterning a second sacrificial material or by an opening formed in a dielectric material through which the interconnect will extend. A portion of the first sacrificial material, exposed within the opening through the dielectric material, along with the second sacrificial material are removed and replaced with conductive material(s) to integrally form the interconnect and the upper conductive structure. The interconnect occupies a volume between vertically overlapping areas of the lower conductive structure and the upper conductive structure, where such overlapping areas coincide with the opening through the dielectric material.

公开(公告)号：US11735261B2

公开(公告)日：2023-08-22

申请号：US17544679

申请日：2021-12-07

Applicant: Micron Technology, Inc.

Inventor： Andrea Redaelli ,  Agostino Pirovano ,  Innocenzo Tortorelli ,  Fabio Pellizzer

IPC: G11C13/00 ,  H10B63/00 ,  H10N70/20 ,  H10N70/00

CPC classification number: G11C13/0069 ,  G11C13/0004 ,  G11C13/004 ,  G11C13/0007 ,  H10B63/80 ,  H10N70/063 ,  H10N70/24 ,  H10N70/884 ,  H10N70/8825 ,  H10N70/8828 ,  G11C2013/0073 ,  G11C2213/52

Abstract: Methods, systems, and devices for programming enhancement in memory cells are described. An asymmetrically shaped memory cell may enhance ion crowding at or near a particular electrode, which may be leveraged for accurately reading a stored value of the memory cell. Programming the memory cell may cause elements within the cell to separate, resulting in ion migration towards a particular electrode. The migration may depend on the polarity of the cell and may create a high resistivity region and low resistivity region within the cell. The memory cell may be sensed by applying a voltage across the cell. The resulting current may then encounter the high resistivity region and low resistivity region, and the orientation of the regions may be representative of a first or a second logic state of the cell.

公开(公告)号：US20230230642A1

公开(公告)日：2023-07-20

申请号：US18189824

申请日：2023-03-24

Applicant: Micron Technology, Inc.

Inventor： Karthik Sarpatwari ,  Fabio Pellizzer ,  Nevil N. Gajera

IPC: G11C16/34 ,  G11C16/26 ,  G11C16/10 ,  G11C16/30

CPC classification number: G11C16/3404 ,  G11C16/26 ,  G11C16/10 ,  G11C16/30

Abstract: Systems, methods and apparatus to determine a programming mode of a set of memory cells that store an indicator of the programming mode. In response to a command to read the memory cells in a memory device, a first read voltage is applied to the memory cells to identify a first subset of the memory cells that become conductive under the first read voltage. The determination of the first subset is configured as an operation common to different programming modes. Based on whether the first subset of the memory cell includes one or more predefined memory cells, the memory device determines a programming mode of memory cells. Once the programming mode is identified from the common operation, the memory device can further execute the command to determine a data item stored, via the programming mode, in the memory cells.

公开(公告)号：US20230171968A1

公开(公告)日：2023-06-01

申请号：US17536927

申请日：2021-11-29

Applicant: Micron Technology, Inc.

Inventor： Srivatsan Venkatesan ,  Fabio Pellizzer

IPC: H01L27/24 ,  H01L45/00

CPC classification number: H01L27/2463 ,  H01L45/16

Abstract: Systems, methods, and apparatus related to spike current suppression in a memory array. In one approach, a memory device includes a memory array having a crosspoint memory architecture. The memory array has access lines (e.g., word lines and/or bit lines) configured to access memory cells of the memory array. Spike current suppression is implemented using a folded access line structure. Each access line includes integrated top and bottom insulating layers that restrict current flow to the memory cells through a narrower middle portion of the access line. For near memory cells located overlying or underlying the insulating layers, the resistance to each memory cell is increased because the cell is accessed using only the higher resistance path of the meandering, folded circuit path that flows through the middle portion. Spike discharge that occurs when the memory cell is selected is reduced by this higher resistance path.

公开(公告)号：US11610634B2

公开(公告)日：2023-03-21

申请号：US17324827

申请日：2021-05-19

Applicant: Micron Technology, Inc.

Inventor： Fabio Pellizzer

IPC: G11C7/00 ,  G11C16/26 ,  G11C16/12 ,  G11C16/30 ,  G11C16/34

Abstract: The present disclosure includes apparatuses, methods, and systems for sensing two memory cells to determine multiple data values. An embodiment includes a memory having a plurality of memory cells and circuitry configured to sense memory states of each of two self-selecting multi-level memory cells (MLC) of the plurality of memory cells to determine multiple data values. The data values are determined by sensing a memory state of a first MLC using a first sensing voltage in a sense window between a first threshold voltage distribution corresponding to a first memory state and a second threshold voltage distribution corresponding to a second memory state and sensing a memory state of a second MLC using a second sensing voltage in a sense window between the first threshold voltage distribution corresponding to a first memory state and a second threshold voltage distribution corresponding to the second memory state. The sequence of determining data values includes sensing the memory state of the first and the second MLCs using higher sensing voltages than the first and the second sensing voltages in subsequent sensing windows, in repeated iterations, until the state of the first and the second MLCs are determined. The first and second sensing voltages are selectably closer in the sense window to the first threshold voltage distribution or the second threshold voltage distribution.