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公开(公告)号：US12131793B2
公开(公告)日：2024-10-29
申请号：US17609577
申请日：2020-10-13
Applicant: Micron Technology, Inc.
Inventor： Agostino Pirovano
CPC classification number: G11C29/789 , G11C16/08 , G11C16/102 , G11C16/24 , G11C29/52
Abstract: Methods, systems, and devices related to 3D self-selecting-memory array of memory cells are described. The method relates to a solution for improving the fault-tolerant capability of memory devices, including: applying a triple-modular-redundancy calculation in a programming phase of the memory cells of a memory array, and adopting a sequence of two opposite dual polarity algorithms applied along a selected bit line and in parallel on the at least three selected word lines of the memory array.
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公开(公告)号：US11869585B2
公开(公告)日：2024-01-09
申请号：US17331610
申请日：2021-05-26
Applicant: Micron Technology, Inc.
Inventor： Mattia Boniardi , Agostino Pirovano , Innocenzo Tortorelli
IPC: G11C13/00
CPC classification number: G11C13/0004 , G11C13/004 , G11C13/0069 , G11C2013/009
Abstract: Methods, systems, and devices for operating memory cell(s) are described. A resistance of a storage element included in a memory cell may be programmed by applying a voltage to the memory cell that causes ion movement within the storage element, where the storage element remains in a single phase and has different resistivity based on a location of the ions within the storage element. In some cases, multiple of such storage elements may be included in a memory cell, where ions within the storage elements respond differently to electric pulses, and a non-binary logic value may be stored in the memory cell by applying a series of voltages or currents to the memory cell.
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公开(公告)号：US11735261B2
公开(公告)日：2023-08-22
申请号：US17544679
申请日：2021-12-07
Applicant: Micron Technology, Inc.
Inventor： Andrea Redaelli , Agostino Pirovano , Innocenzo Tortorelli , Fabio Pellizzer
CPC classification number: G11C13/0069 , G11C13/0004 , G11C13/004 , G11C13/0007 , H10B63/80 , H10N70/063 , H10N70/24 , H10N70/884 , H10N70/8825 , H10N70/8828 , G11C2013/0073 , G11C2213/52
Abstract: Methods, systems, and devices for programming enhancement in memory cells are described. An asymmetrically shaped memory cell may enhance ion crowding at or near a particular electrode, which may be leveraged for accurately reading a stored value of the memory cell. Programming the memory cell may cause elements within the cell to separate, resulting in ion migration towards a particular electrode. The migration may depend on the polarity of the cell and may create a high resistivity region and low resistivity region within the cell. The memory cell may be sensed by applying a voltage across the cell. The resulting current may then encounter the high resistivity region and low resistivity region, and the orientation of the regions may be representative of a first or a second logic state of the cell.
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公开(公告)号：US20230027799A1
公开(公告)日：2023-01-26
申请号：US17881274
申请日：2022-08-04
Applicant: Micron Technology, Inc.
Inventor： Stephen W. Russell , Andrea Redaelli , Innocenzo Tortorelli , Agostino Pirovano , Fabio Pellizzer , Lorenzo Fratin
Abstract: Methods, systems, and devices for techniques for forming self-aligned memory structures are described. Aspects include etching a layered assembly of materials including a first conductive material and a first sacrificial material to form a first set of channels along a first direction that creates a first set of sections. An insulative material may be deposited within each of the first set of channels and a second sacrificial material may be deposited onto the first set of sections and the insulating material. A second set of channels may be etched into the layered assembly of materials along a second direction that creates a second set of sections, where the second set of channels extend through the first and second sacrificial materials. Insulating material may be deposited in the second set of channels and the sacrificial materials removed leaving a cavity. A memory material may be deposited in the cavity.
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公开(公告)号：US20220366974A1
公开(公告)日：2022-11-17
申请号：US17816612
申请日：2022-08-01
Applicant: Micron Technology, Inc.
Inventor： Innocenzo Tortorelli , Russell L. Meyer , Agostino Pirovano , Andrea Redaelli , Lorenzo Fratin , Fabio Pellizzer
Abstract: Disclosed herein is a memory cell including a memory element and a selector device. Data may be stored in both the memory element and selector device. The memory cell may be programmed by applying write pulses having different polarities and magnitudes. Different polarities of the write pulses may program different logic states into the selector device. Different magnitudes of the write pulses may program different logic states into the memory element. The memory cell may be read by read pulses all having the same polarity. The logic state of the memory cell may be detected by observing different threshold voltages when the read pulses are applied. The different threshold voltages may be responsive to the different polarities and magnitudes of the write pulses.
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Patent Agency Ranking
公开(公告)号：US11374059B2
公开(公告)日：2022-06-28
申请号：US16892459
申请日：2020-06-04
Applicant: Micron Technology, Inc.
Inventor： Fabio Pellizzer , Andrea Redaelli , Agostino Pirovano , Innocenzo Tortorelli
Abstract: The present disclosure includes memory cells having resistors, and methods of forming the same. An example method includes forming a first conductive line, forming a second conductive line, and forming a memory element between the first conductive line and the second conductive line. Forming the memory element can include forming one or more memory materials, and forming a resistor in series with the one or more memory materials. The resistor can be configured to reduce a capacitive discharge through the memory element during a state transition of the memory element.
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公开(公告)号：US20220122663A1
公开(公告)日：2022-04-21
申请号：US17511484
申请日：2021-10-26
Applicant: Micron Technology, Inc.
Inventor： Agostino Pirovano , Fabio Pellizzer
Abstract: Methods, systems, and devices for polarity-written cell architectures for a memory device are described. In an example, the described architectures may include memory cells that each include or are otherwise associated with a material configured to store one of a set of logic states based at least in part on a polarity of a write voltage applied to the material. Each of the memory cells may also include a cell selection component configured to selectively couple the material with an access line. In some examples, the material may include a chalcogenide, and the material may be configured to store each of the set of logic states in an amorphous state of the chalcogenide. In various examples, different logic states may be associated with different compositional distributions of the material of a respective memory cell, different threshold characteristics of the material of a respective memory cell, or other characteristics.
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公开(公告)号：US11302393B2
公开(公告)日：2022-04-12
申请号：US17024248
申请日：2020-09-17
Applicant: Micron Technology, Inc.
Inventor： Hernan A. Castro , Innocenzo Tortorelli , Agostino Pirovano , Fabio Pellizzer
Abstract: Techniques are provided for programming a self-selecting memory cell that stores a first logic state. To program the memory cell, a pulse having a first polarity may be applied to the cell, which may result in the memory cell having a reduced threshold voltage. During a duration in which the threshold voltage of the memory cell may be reduced (e.g., during a selection time), a second pulse having a second polarity (e.g., a different polarity) may be applied to the memory cell. Applying the second pulse to the memory cell may result in the memory cell storing a second logic state different than the first logic state.
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公开(公告)号：US20210366541A1
公开(公告)日：2021-11-25
申请号：US17331610
申请日：2021-05-26
Applicant: Micron Technology, Inc.
Inventor： Mattia Boniardi , Agostino Pirovano , Innocenzo Tortorelli
IPC: G11C13/00
Abstract: Methods, systems, and devices for operating memory cell(s) are described. A resistance of a storage element included in a memory cell may be programmed by applying a voltage to the memory cell that causes ion movement within the storage element, where the storage element remains in a single phase and has different resistivity based on a location of the ions within the storage element. In some cases, multiple of such storage elements may be included in a memory cell, where ions within the storage elements respond differently to electric pulses, and a non-binary logic value may be stored in the memory cell by applying a series of voltages or currents to the memory cell.
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公开(公告)号：US11152065B2
公开(公告)日：2021-10-19
申请号：US16863175
申请日：2020-04-30
Applicant: Micron Technology, Inc.
Inventor： Innocenzo Tortorelli , Andrea Redaelli , Agostino Pirovano , Fabio Pellizzer , Mario Allegra , Paolo Fantini
Abstract: Methods, systems, and devices related to techniques to access a self-selecting memory device are described. A self-selecting memory cell may store one or more bits of data represented by different threshold voltages of the self-selecting memory cell. A programming pulse may be varied to establish the different threshold voltages by modifying one or more time durations during which a fixed level of voltage or current is maintained across the self-selecting memory cell. The self-selecting memory cell may include a chalcogenide alloy. A non-uniform distribution of an element in the chalcogenide alloy may determine a particular threshold voltage of the self-selecting memory cell. The shape of the programming pulse may be configured to modify a distribution of the element in the chalcogenide alloy based on a desired logic state of the self-selecting memory cell.
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