知搜-全球专利检索

  1. Login
  2. Sign Up

Search Results

69 records (took 0.055 seconds)

    Analog storage using memory device
    1.
    发明授权
    Analog storage using memory device 有权

    公开(公告)号：US12080365B2

    公开(公告)日：2024-09-03

    申请号：US17048669

    申请日：2020-01-28

    Applicant: Micron Technology, Inc.

    Inventor： Mattia Boniardi ,  Innocenzo Tortorelli

    IPC: G11C27/00 ,  G06N3/065 ,  G06N3/08

    CPC classification number: G11C27/005 ,  G06N3/065 ,  G06N3/08

    Abstract: Methods, systems, and devices for analog storing information are described herein. Such methods, systems and devices are suitable for synaptic weight storage in electronic neuro-biological mimicking architectures. A memory device may include a plurality of memory cells each respective memory cell in the plurality of memory cells with a respective programming sensitivity different from the respective programming sensitivity of other memory cells in the plurality. Memory cells may be provided on different decks of a multi-deck memory array. A storage element material of a respective memory cell may have a thickness and/or a composition different from another thickness or composition of a respective storage element material of another respective memory cell on a different deck in the multi-deck memory array. The memory device may further include reading circuitry configured to analogically read respective information programmed in the respective memory cells and to provide an output based on a combination of the respective information analogically read from the respective memory cells.

    Pulse based multi-level cell programming
    2.
    发明授权
    Pulse based multi-level cell programming 有权

    公开(公告)号：US11984191B2

    公开(公告)日：2024-05-14

    申请号：US17740069

    申请日：2022-05-09

    Applicant: Micron Technology, Inc.

    Inventor： Hernan A. Castro ,  Mattia Boniardi ,  Innocenzo Tortorelli

    IPC: G11C8/00 ,  G11C7/10 ,  G11C16/34

    CPC classification number: G11C7/1039 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/1087 ,  G11C7/1093 ,  G11C16/3404

    Abstract: Methods, systems, and devices for pulse based multi-level cell programming are described. A memory device may identify an intermediate logic state to store to a multi-level memory cell capable of storing three or more logic states. The memory device may apply a first pulse with a first polarity to the memory cell to store a SET or RESET state to the memory cell based on identifying the intermediate logic state. As such, the memory device may identify a threshold voltage of the memory cell that stores the SET or RESET state. The memory device may apply a quantity of pulses to the memory cell to store the identified intermediate logic state based on identifying the threshold voltage of the memory cell that stores the SET or RESET state. In some examples, the quantity of pulses may have a second polarity different than the first polarity.

    ANALOG STORAGE USING MEMORY DEVICE
    3.
    发明申请
    ANALOG STORAGE USING MEMORY DEVICE 有权

    公开(公告)号：US20230114966A1

    公开(公告)日：2023-04-13

    申请号：US17048669

    申请日：2020-01-28

    Applicant: Micron Technology, Inc.

    Inventor： Mattia Boniardi ,  Innocenzo Tortorelli

    IPC: G11C27/00 ,  G06N3/08 ,  G06N3/065

    Abstract: Methods, systems, and devices for analog storing information are described herein. Such methods, systems and devices are suitable for synaptic weight storage in electronic neuro-biological mimicking architectures. A memory device may include a plurality of memory cells each respective memory cell in the plurality of memory cells with a respective programming sensitivity different from the respective programming sensitivity of other memory cells in the plurality. Memory cells may be provided on different decks of a multi-deck memory array. A storage element material of a respective memory cell may have a thickness and/or a composition different from another thickness or composition of a respective storage element material of another respective memory cell on a different deck in the multi-deck memory array. The memory device may further include reading circuitry configured to analogically read respective information programmed in the respective memory cells and to provide an output based on a combination of the respective information analogically read from the respective memory cells.

    MEMORY CELLS FOR STORING OPERATIONAL DATA
    5.
    发明申请
    MEMORY CELLS FOR STORING OPERATIONAL DATA 有权

    公开(公告)号：US20220172782A1

    公开(公告)日：2022-06-02

    申请号：US17108783

    申请日：2020-12-01

    Applicant: Micron Technology, Inc.

    Inventor： Mattia Boniardi ,  Anna Maria Conti ,  Innocenzo Tortorelli

    IPC: G11C16/10 ,  G11C16/26 ,  G11C16/30 ,  G11C16/34

    Abstract: Methods, systems, and devices for memory cells for storing operational data are described. A memory device may include an array of memory cells with different sets of cells for storing data. A first set of memory cells may store data for operating the memory device, and the associated memory cells may each contain a chalcogenide storage element. A second set of memory cells may store host data. Some memory cells included in the first set may be programmed to store a first logic state and other memory cells in the first set may be left unprogrammed (and may represent a second logic state). Sense circuitry may be coupled with the array and may determine a value of data stored by the first set of memory cells.

    ADAPTIVE WRITE OPERATIONS FOR A MEMORY DEVICE
    7.
    发明申请
    ADAPTIVE WRITE OPERATIONS FOR A MEMORY DEVICE 有权

    公开(公告)号：US20210027813A1

    公开(公告)日：2021-01-28

    申请号：US16518876

    申请日：2019-07-22

    Applicant: Micron Technology, Inc.

    Inventor： Mattia Boniardi ,  Richard K. Dodge ,  Innocenzo Tortorelli ,  Mattia Robustelli ,  Mario Allegra

    IPC: G11C7/10

    Abstract: Methods, systems, and devices for adaptive write operations for a memory device are described. In an example, the described techniques may include identifying a quantity of access operations performed on a memory array, modifying one or more parameters for a write operation based on the identified quantity of access operations, and writing logic states to the memory array by performing the write operation according to the one or more modified parameters. In some examples, the memory array may include memory cells associated with a configurable material element, such as a chalcogenide material, that stores a logic state based on a material property of the material element. In some examples, the described techniques may at least partially compensate for a change in memory material properties due to aging or other degradation or changes over time (e.g., due to accumulated access operations).

    Memory cell architecture for multilevel cell programming
    8.
    发明授权
    Memory cell architecture for multilevel cell programming 有权

    公开(公告)号：US10311954B2

    公开(公告)日：2019-06-04

    申请号：US16045526

    申请日：2018-07-25

    Applicant: Micron Technology, Inc.

    Inventor： Mario Allegra ,  Mattia Boniardi

    IPC: G11C11/00 ,  G11C13/00 ,  G11C11/56 ,  H01L45/00 ,  H01L27/24

    Abstract: Methods, systems, and devices for operating and forming a multilevel memory cell and array are described. A multilevel memory cell includes two or more binary memory elements, which may include phase change material. Each memory element may be programmed to one of two possible states—e.g., a fully amorphous state or a fully crystalline state. By combining multiple binary memory elements in a single memory cell, the memory cell may be programmed to store more than two states. The different memory elements may be programmed by selectively melting each memory element. Selective melting may be controlled by using memory elements with different melting temperatures or using electrodes with different electrical resistances, or both.

Patent Agency Ranking