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    CROSS-POINT PILLAR ARCHITECTURE FOR MEMORY ARRAYS
    2.
    发明公开
    CROSS-POINT PILLAR ARCHITECTURE FOR MEMORY ARRAYS 审中-公开

    公开(公告)号：US20240221829A1

    公开(公告)日：2024-07-04

    申请号：US18409992

    申请日：2024-01-11

    Applicant: Micron Technology, Inc.

    Inventor： Innocenzo Tortorelli ,  Fabio Pellizzer ,  Mattia Robustelli ,  Alessandro Sebastiani

    IPC: G11C13/00

    CPC classification number: G11C13/003 ,  G11C13/0004 ,  G11C13/0023 ,  G11C13/004 ,  G11C13/0069 ,  G11C2213/71

    Abstract: Methods, systems, and devices for a cross-point pillar architecture for memory arrays are described. Multiple selector devices may be configured to access or activate a pillar within a memory array, where the selector devices may each be or include a chalcogenide material. A pillar access line may be coupled with multiple selector devices, where each selector device may correspond to a pillar associated with the pillar access line. Pillar access lines on top and bottom of the pillars of the memory array may be aligned in a square or rectangle formation, or in a hexagonal formation. Pillars and corresponding selector devices on top and bottom of the pillars may be located at overlapping portions of the pillar access lines, thereby forming a cross point architecture for pillar selection or activation. The selector devices may act in pairs to select or activate a pillar upon application of a respective selection voltage.

    MEMORY AND STORAGE ON A SINGLE CHIP
    3.
    发明公开
    MEMORY AND STORAGE ON A SINGLE CHIP 审中-公开

    公开(公告)号：US20240130143A1

    公开(公告)日：2024-04-18

    申请号：US17968744

    申请日：2022-10-18

    Applicant: Micron Technology, Inc.

    Inventor： Innocenzo Tortorelli ,  Agostino Pirovano ,  Matteo Impalà ,  Mattia Robustelli ,  Fabio Pellizzer

    IPC: H01L27/24 ,  H01L45/00

    CPC classification number: H01L27/2481 ,  H01L45/06 ,  H01L45/143 ,  H01L45/1683

    Abstract: A single memory chip including both memory and storage capabilities on the single chip and accompanying process for forming a memory array including both capabilities is disclosed. In particular, the single chip may incorporate the use of two different chalcogenide materials deposited thereon to implement the memory and storage capabilities. Chalcogenide materials provide flexibility on cell performance, such as by changing the chalcogenide material composition. For the single memory chip, one type of chalcogenide material may be utilized to create memory cells and another type of chalcogenide material may be utilized to create storage cells. The process for forming the memory array includes forming first and second openings in a starting structure and performing a series of etching and deposition steps on the structure to form the memory and storage cells using the two different chalcogenide compositions. The memory and storage cells are independently addressable via wordline and bitline selection.

    ASYMMETRIC MEMORY CELL DESIGN
    4.
    发明公开
    ASYMMETRIC MEMORY CELL DESIGN 审中-公开

    公开(公告)号：US20230354619A1

    公开(公告)日：2023-11-02

    申请号：US17818923

    申请日：2022-08-10

    Applicant: Micron Technology, Inc.

    Inventor： Mattia Robustelli ,  Innocenzo Tortorelli

    IPC: H01L27/24 ,  H01L45/00

    CPC classification number: H01L27/249 ,  H01L45/06 ,  H01L45/1253 ,  H01L45/141 ,  H01L45/1683

    Abstract: Methods, systems, and devices for asymmetric memory cell design are described. A memory device may implement a programming scheme that uses low programming pulses based on an asymmetric memory cell design. For example, the asymmetric memory cells may have electrodes with different contact areas (e.g., widths) and may accordingly be biased to a desired polarity (e.g., negative biased or positive biased) for programming operations. That is, the asymmetric memory cell design may enable an asymmetric read window budget. For example, an asymmetric memory cell may be polarity biased, supporting programming operations for logic states based on the polarity bias.

    TECHNIQUES FOR PROGRAMMING MULTI-LEVEL SELF-SELECTING MEMORY CELL
    6.
    发明申请
    TECHNIQUES FOR PROGRAMMING MULTI-LEVEL SELF-SELECTING MEMORY CELL 有权

    公开(公告)号：US20220262437A1

    公开(公告)日：2022-08-18

    申请号：US17735598

    申请日：2022-05-03

    Applicant: Micron Technology, Inc.

    Inventor： Mattia Robustelli

    IPC: G11C13/00 ,  G11C11/402 ,  G11C11/4074 ,  G11C11/56

    Abstract: Techniques are provided for programming a multi-level self-selecting memory cell that includes a chalcogenide material. To program one or more intermediate memory states to the self-selecting memory cell, a programming pulse sequence that includes two pulses may be used. A first pulse of the programming pulse sequence may have a first polarity and a first magnitude and the second pulse of the programming pulse sequence may have a second polarity different than the first polarity and a second magnitude different than the first magnitude. After applying both pulses in the programming pulse sequence, the self-selecting memory cell may store an intermediate state that represents two bits of data (e.g., a logic ‘01’ or a logic ‘10’).

    ADAPTIVE WRITE OPERATIONS FOR A MEMORY DEVICE
    8.
    发明申请
    ADAPTIVE WRITE OPERATIONS FOR A MEMORY DEVICE 有权

    公开(公告)号：US20210027813A1

    公开(公告)日：2021-01-28

    申请号：US16518876

    申请日：2019-07-22

    Applicant: Micron Technology, Inc.

    Inventor： Mattia Boniardi ,  Richard K. Dodge ,  Innocenzo Tortorelli ,  Mattia Robustelli ,  Mario Allegra

    IPC: G11C7/10

    Abstract: Methods, systems, and devices for adaptive write operations for a memory device are described. In an example, the described techniques may include identifying a quantity of access operations performed on a memory array, modifying one or more parameters for a write operation based on the identified quantity of access operations, and writing logic states to the memory array by performing the write operation according to the one or more modified parameters. In some examples, the memory array may include memory cells associated with a configurable material element, such as a chalcogenide material, that stores a logic state based on a material property of the material element. In some examples, the described techniques may at least partially compensate for a change in memory material properties due to aging or other degradation or changes over time (e.g., due to accumulated access operations).

    ADAPTIVE WRITE OPERATIONS FOR A MEMORY DEVICE
    10.
    发明公开
    ADAPTIVE WRITE OPERATIONS FOR A MEMORY DEVICE 审中-公开

    公开(公告)号：US20240203468A1

    公开(公告)日：2024-06-20

    申请号：US18593635

    申请日：2024-03-01

    Applicant: Micron Technology, Inc.

    Inventor： Mattia Boniardi ,  Richard K. Dodge ,  Innocenzo Tortorelli ,  Mattia Robustelli ,  Mario Allegra

    IPC: G11C7/10

    CPC classification number: G11C7/1096 ,  G11C7/1051

    Abstract: Methods, systems, and devices for adaptive write operations for a memory device are described. In an example, the described techniques may include identifying a quantity of access operations performed on a memory array, modifying one or more parameters for a write operation based on the identified quantity of access operations, and writing logic states to the memory array by performing the write operation according to the one or more modified parameters. In some examples, the memory array may include memory cells associated with a configurable material element, such as a chalcogenide material, that stores a logic state based on a material property of the material element. In some examples, the described techniques may at least partially compensate for a change in memory material properties due to aging or other degradation or changes over time (e.g., due to accumulated access operations).

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