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    Cross-point pillar architecture for memory arrays
    4.
    发明授权
    Cross-point pillar architecture for memory arrays 有权

    公开(公告)号：US11887661B2

    公开(公告)日：2024-01-30

    申请号：US17647578

    申请日：2022-01-10

    Applicant: Micron Technology, Inc.

    Inventor： Innocenzo Tortorelli ,  Fabio Pellizzer ,  Mattia Robustelli ,  Alessandro Sebastiani

    IPC: G11C13/00

    CPC classification number: G11C13/003 ,  G11C13/0004 ,  G11C13/004 ,  G11C13/0023 ,  G11C13/0069 ,  G11C2213/71

    Abstract: Methods, systems, and devices for a cross-point pillar architecture for memory arrays are described. Multiple selector devices may be configured to access or activate a pillar within a memory array, where the selector devices may each be or include a chalcogenide material. A pillar access line may be coupled with multiple selector devices, where each selector device may correspond to a pillar associated with the pillar access line. Pillar access lines on top and bottom of the pillars of the memory array may be aligned in a square or rectangle formation, or in a hexagonal formation. Pillars and corresponding selector devices on top and bottom of the pillars may be located at overlapping portions of the pillar access lines, thereby forming a cross point architecture for pillar selection or activation. The selector devices may act in pairs to select or activate a pillar upon application of a respective selection voltage.

    RAMP-BASED BIASING IN A MEMORY DEVICE
    5.
    发明公开
    RAMP-BASED BIASING IN A MEMORY DEVICE 审中-公开

    公开(公告)号：US20230402094A1

    公开(公告)日：2023-12-14

    申请号：US18457188

    申请日：2023-08-28

    Applicant: Micron Technology, Inc.

    Inventor： Hari Giduturi

    IPC: G11C13/00 ,  G11C11/16

    CPC classification number: G11C13/003 ,  G11C13/0023 ,  G11C11/1659 ,  G11C11/1653

    Abstract: Methods and systems include memory devices with multiple access lines arranged in an array to form a multiple intersections. Memory cells are located at the intersections of the multiple access lines. Decoders are configured to drive the multiple memory cells via the multiple access lines. Variable biasing circuitry may bias a voltage on an access line of the multiple access lines to change a variable ramp rate of the voltage on the access line. A control circuit is configured to determine a memory cell of the multiple memory cells to be activated. Based at least in part on a distance from the memory cell to a corresponding decoder, the control circuit may set the variable ramp rate of the biasing circuitry.

    Extended memory communication
    7.
    发明授权
    Extended memory communication 有权

    公开(公告)号：US11810618B2

    公开(公告)日：2023-11-07

    申请号：US17453136

    申请日：2021-11-01

    Applicant: Micron Technology, Inc.

    Inventor： Vijay S. Ramesh ,  Allan Porterfield

    IPC: G11C11/00 ,  G11C13/00 ,  G06F9/54 ,  G06F9/30 ,  G06F7/57

    CPC classification number: G11C13/0023 ,  G06F7/57 ,  G06F9/3001 ,  G06F9/542 ,  G06F9/546 ,  G11C13/004 ,  G11C13/0069 ,  G11C2213/71

    Abstract: Systems, apparatuses, and methods related to extended memory communication subsystems for performing extended memory operations are described. An example method can include receiving, at a processing unit that is coupled between a host device and a non-volatile memory device, signaling indicative of a plurality of operations to be performed on data written to or read from the non-volatile memory device. The method can further include performing, at the processing unit, at least one operation of the plurality of operations in response to the signaling. The method can further include accessing a portion of a memory array in the non-volatile memory device. The method can further include transmitting additional signaling indicative of a command to perform one or more additional operations of the plurality of operations on the data written to or read from the non-volatile memory device.

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