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    Phase charge sharing
    2.
    发明授权
    Phase charge sharing 有权

    公开(公告)号：US11087829B2

    公开(公告)日：2021-08-10

    申请号：US16926476

    申请日：2020-07-10

    申请人： Micron Technology, Inc.

    发明人： James S. Rehmeyer ,  George B. Raad ,  Debra M. Bell ,  Markus H. Geiger ,  Anthony D. Veches

    IPC分类号： G11C11/4094 ,  G11C11/408 ,  G11C11/4096 ,  G11C11/406

    摘要： Methods, systems, and devices for phase charge sharing are described. In some memory systems or memory devices, one or more decoders may be used to bias access lines of a memory die. The decoders may transfer voltage or current between a first conductive line of the decoder and a second conductive line of the decoder via a shorting device. Transferring the voltage or current may be performed as part of or in association with an operation (e.g., an activate or pre-charge operation) to access one or more memory cells of the memory die. In some examples, the decoders may transfer voltage or current between a first conductive line of a decoder associated with a first refresh activity and a second conductive line of the decoder associated with a second refresh activity via a shorting device.

    Data storage based on data polarity
    4.
    发明授权
    Data storage based on data polarity 有权

    公开(公告)号：US10832768B2

    公开(公告)日：2020-11-10

    申请号：US16459462

    申请日：2019-07-01

    申请人： Micron Technology, Inc.

    发明人： John F. Schreck ,  George B. Raad

    IPC分类号： G11C16/06 ,  G11C11/56 ,  G11C29/42 ,  G06F3/06 ,  G06F13/16

    摘要： Methods, systems, and devices for storing and reading data at a memory device are described. A memory device may utilize one or more storage states to store data within a data word. The memory device may exhibit higher data leakage or more power consumption when storing or reading a first storage state compared to storing or reading one or more other storage states. In some cases, the memory device may generate a second data word corresponding to a first data word by modifying each symbol type of the first data word to generate a different symbol type for the second data word. A memory device may reduce the occurrence of a storage state associated with large data leakage, or high-power consumption, or both. Further, the memory device may generate and store an indicator indicating the transformation of a corresponding data word.

    MEMORY DEVICE WITH A CHARGE TRANSFER DEVICE
    6.
    发明申请
    MEMORY DEVICE WITH A CHARGE TRANSFER DEVICE 审中-公开

    公开(公告)号：US20200211639A1

    公开(公告)日：2020-07-02

    申请号：US16232347

    申请日：2018-12-26

    申请人： Micron Technology, Inc.

    发明人： George B. Raad ,  John F. Schreck

    IPC分类号： G11C11/56

    摘要： Techniques are provided for sensing a signal associated with a memory cell capable of storing three or more logic states. To sense a state of the memory cell, a charge may be transferred between a digit line and a node coupled with a plurality of sense components using a charge transfer device. Once the charge is transferred, one or more of the plurality of sense components may sense the charge with one of a variety of sensing schemes. Based on the charge being transferred using the charge transfer device and each sense component sensing the charge, a logic state associated with the memory cell may be determined. The number of sensed states may be correlated to the number of sense amplifiers. The ratio of the number of states read by the first sense component and the second sense component to the number of sense components may be greater than one.

    SENSE ARCHITECTURE
    7.
    发明申请
    SENSE ARCHITECTURE 审中-公开

    公开(公告)号：US20200211604A1

    公开(公告)日：2020-07-02

    申请号：US16232916

    申请日：2018-12-26

    申请人： Micron Technology, Inc.

    发明人： George B. Raad ,  John F. Schreck

    IPC分类号： G11C7/08 ,  G11C7/06 ,  G11C7/10

    摘要： Devices and methods for a sensing scheme are described. A device may include a memory array and a column select line configured to couple with a single page of a set of pages within the memory array when the single page is selected during an access operation. The column select line may be isolated from other pages (e.g., unselected pages) of the set. The device may include a set of sense component groups coupled with the single page. Each sense component group of the set may be configured to access one or more memory cells of the single page using the column select line. The device may include a decoding component configured to couple a sense component group of the set with an I/O line of an I/O channel. The device may communicate information with the I/O line during the access operation.

    METHODS FOR INDEPENDENT MEMORY BANK MAINTENANCE AND MEMORY DEVICES AND SYSTEMS EMPLOYING THE SAME
    9.
    发明申请
    METHODS FOR INDEPENDENT MEMORY BANK MAINTENANCE AND MEMORY DEVICES AND SYSTEMS EMPLOYING THE SAME 审中-公开

    公开(公告)号：US20190371392A1

    公开(公告)日：2019-12-05

    申请号：US16543477

    申请日：2019-08-16

    申请人： Micron Technology, Inc.

    发明人： George B. Raad ,  Jonathan S. Parry ,  James S. Rehmeyer ,  Timothy B. Cowles

    IPC分类号： G11C11/406

    摘要： Memory devices, systems including memory devices, and methods of operating memory devices in which multiple counters are provided to permit memory refresh commands greater freedom in targeting subsets of the memory device for data refresh operations. In one embodiment, a memory device is provided, comprising a plurality of memory banks, and circuitry configured to (i) store a plurality of values, each of the plurality of values corresponding to one of the plurality of memory banks; (ii) refresh first data stored in a first one of the plurality of memory banks; and (iii) update a first one of the plurality of values corresponding to the first one of the plurality of memory banks based at least in part on refreshing the first data.