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公开(公告)号：US20240177743A1
公开(公告)日：2024-05-30
申请号：US18431676
申请日：2024-02-02
CPC分类号： G11C5/025 , G11C5/04 , G11C29/50004 , G11C29/50012 , G11C2029/5002 , G11C2029/5004 , G11C2029/5006
摘要： Methods of optimizing the placement of memories in a memory device including a substrate and an electrical component, and associated devices and systems, are disclosed herein. A representative method includes first testing the memories to determine at least one parameter for each of the memories indicating an ability of the memory to process signals from the electrical component. The method can further include labeling each memory with a label based on the parameter, the labels including at least a first label and a second label. The first label can indicate that the memories with the first label are better able to process signals from the electrical component than the memories with the second label. The method can further include electrically coupling the memories to the substrate such that the memories with the second label are positioned closer to the electrical component than the memories with the first label.
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公开(公告)号：US11783909B2
公开(公告)日：2023-10-10
申请号：US17876769
申请日：2022-07-29
IPC分类号： G11C29/44 , G11C11/408
CPC分类号： G11C29/4401 , G11C11/4087
摘要： A memory device includes a memory bank that includes a first set of memory rows in a first section of the memory bank, a first set of redundant rows in a first section of the memory bank, a second set of memory rows in a second section of the memory bank, and a second set of redundant rows in the second section of the memory bank. The memory bank also includes a repeater blocker circuit that when in operation selectively blocks a signal from transmission to the second section of the memory bank and blocker control circuitry that when in operation transmits a control signal to control the selective blocking of the signal by the repeater blocker circuit.
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公开(公告)号：US11769561B2
公开(公告)日：2023-09-26
申请号：US17119509
申请日：2020-12-11
IPC分类号： G11C17/00 , G11C17/08 , G11C17/16 , G11C17/18 , G11C16/08 , G11C16/22 , G11C11/22 , G11C13/00 , G11C11/16
CPC分类号： G11C17/08 , G11C11/1653 , G11C11/1695 , G11C11/2253 , G11C11/2295 , G11C13/0004 , G11C13/0023 , G11C13/0059 , G11C16/08 , G11C16/22 , G11C17/165 , G11C17/18
摘要： Memory devices, systems including memory devices, and methods of operating memory devices and systems are provided, in which at least a subset of a non-volatile memory array is configured to behave as read-only memory by not implementing erase or write commands. In one embodiment of the present technology, a memory device is provided, comprising a non-volatile memory array, and circuitry configured to store one or more addresses of the non-volatile memory array, to compare an address of a received command to the one or more addresses, and at least in part based on the comparison, determine not to implement the received command. The circuitry can be further configured to return an error message after determining not to implement the received command.
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公开(公告)号：US11694762B2
公开(公告)日：2023-07-04
申请号：US17466160
申请日：2021-09-03
IPC分类号： G11C7/00 , G11C29/44 , G11C29/02 , G11C29/00 , H03M13/11 , G11C11/409 , H03M13/13 , G11C29/18
CPC分类号： G11C29/44 , G11C11/409 , G11C29/027 , G11C29/18 , G11C29/789 , H03M13/1105 , H03M13/13
摘要： Methods, apparatuses and systems related to managing repair assets are described. An apparatus stores a repair segment locator and a repair address for each defect repair. The apparatus may be configured to selectively apply a repair asset to one of multiple sections according to the repair segment locator.
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公开(公告)号：US11682435B2
公开(公告)日：2023-06-20
申请号：US17811153
申请日：2022-07-07
发明人： Di Wu , Debra M. Bell , Anthony D. Veches , James S. Rehmeyer , Libo Wang
IPC分类号： G11C7/22 , G11C7/10 , G11C8/10 , G11C11/4096 , G11C11/4076 , G11C11/406
CPC分类号： G11C7/22 , G11C7/1045 , G11C7/1051 , G11C7/1078 , G11C8/10 , G11C11/4076 , G11C11/4096 , G11C11/40603
摘要： Tracking circuitry may be used to determine if commands and/or command sequences include illegal commands and/or illegal command sequences. If the commands and/or command sequences include illegal commands and/or illegal command sequences, the tracking circuitry may activate signals that prevent execution of the commands and/or notice of the detected illegal commands and/or command sequences.
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公开(公告)号：US20230128914A1
公开(公告)日：2023-04-27
申请号：US17509989
申请日：2021-10-25
IPC分类号： G06F3/06
摘要： Signaling indicative of a command to initialize a plurality of memory dies of a memory device can be received by the memory device. Initialization of a memory die of the memory device can be delayed, at the memory die and based at least in part on fuse states of an array of fuses of the memory die, by an amount of time relative to receipt of the signaling by the memory device. Delaying initialization of memory dies of the memory device in a staggered or asynchronous manner can evenly distribute power consumption of the memory dies so that the likelihood of an associated power spike is reduced or eliminated.
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公开(公告)号：US11449267B1
公开(公告)日：2022-09-20
申请号：US17243357
申请日：2021-04-28
IPC分类号： G06F3/06
摘要： Methods, systems, and apparatuses related to determination of durations of memory device temperatures are described. For example, a controller can be coupled to a memory device to monitor an operating temperature of the memory device. The controller can determine the operating temperature exceeds a threshold temperature. The controller can determine a duration that the temperature exceeds the threshold temperature. The controller can provide data corresponding to the operating temperature and the duration to a requesting device.
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公开(公告)号：US20220238166A1
公开(公告)日：2022-07-28
申请号：US17158490
申请日：2021-01-26
摘要： Dynamic trim selection based on operating voltage levels for semiconductor devices and associated methods and systems are disclosed. Certain semiconductor devices are expected to operate under two or more operating voltage levels. In some embodiments, the semiconductor device can be characterized to determine optimum timing and/or voltage conditions across multiple operating voltage levels. Consequently, multiple sets of timing and/or voltage conditions can be identified depending on the operating voltage levels, which can be stored in a non-volatile memory (NVM) array of the semiconductor device. During operation, the semiconductor device can determine the operating voltage level currently supplied to the semiconductor device and select one of the timing and/or voltage conditions stored in the NVM array such that the semiconductor device can operate with the optimum timing and/or voltage conditions that has been predetermined for the semiconductor device operating under the operating voltage level.
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公开(公告)号：US20220147131A1
公开(公告)日：2022-05-12
申请号：US17094579
申请日：2020-11-10
IPC分类号： G06F1/3203 , G11C11/4074
摘要： Methods, systems, and devices for power management for a memory device are described. For example, a memory device may include one or more memory dies and may be configured to operate using a first supply voltage and a second supply voltage. The first supply voltage may be associated with a first defined voltage range, and the second supply voltage may be associated with a second defined voltage range. The memory device may include a power management integrated circuit (PMIC) that is coupled with the one or more memory dies and provides the supply voltages to the one or more memory dies. The PMIC may be configured to provide, to the one or more memory dies, a first voltage that is within the first defined voltage range as the first supply voltage and a second voltage that is outside the second defined voltage range as the second supply voltage.
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公开(公告)号：US20220139492A1
公开(公告)日：2022-05-05
申请号：US17647508
申请日：2022-01-10
IPC分类号： G11C29/00 , G11C11/408
摘要： Memory devices are disclosed. A device may include a number of memory banks and a number of latch sets, wherein each latch set is associated with a memory bank. The device may also include a fuse array including a number of fuses. The device may further include circuitry configured to read data from a first set of fuses of the number of fuses and broadcast data from the first set of fuses to a first latch set of the number of latch sets. Further, in response to a repair result associated with the first set of fuses being a first state, the circuitry may be configured to read a second set of fuses and broadcast the second set of fuses to the first latch set. Methods of operating a memory device, microelectronic devices, semiconductor devices, and electronic systems are also disclosed.
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