公开(公告)号：US12131174B2

公开(公告)日：2024-10-29

申请号：US17363634

申请日：2021-06-30

申请人： International Business Machines Corporation

发明人： Harish Bharti ,  Rajesh Kumar Saxena ,  Sandeep Sukhija ,  Deepak Bajaj

IPC分类号： G06F9/455 ,  G06F1/3203 ,  G06F9/50 ,  G06F17/18 ,  H04L41/0895 ,  H04L41/50

CPC分类号： G06F9/45558 ,  G06F1/3203 ,  G06F9/5077 ,  G06F17/18 ,  H04L41/0895 ,  H04L41/50 ,  G06F2009/45595

摘要： A system, method, and computer program product for determining “impact quantify measure-based” service chains cross interferences. The method includes quantifying the impact of one service chain on another service chain and to what extent so as facilitate making an informed decision whether to garner more resources and to fine tune the computational services for the service chain. There is further provided beforehand a certainty of required computational resources and the providing the impact or interferences details of one service chain on another helps in minimization of service quality degradation failures. The framework further runs a method step to apply a mutual convexity method on service chains to aid in forecasting cross interferences between chains and includes a step wherein, interferences between both dependent and independent service chain is calculated and provided. The provided interferences calculated result set will ensure while provisioning of virtual network functions doesn't consume energy excessively.

公开(公告)号：US12124310B2

公开(公告)日：2024-10-22

申请号：US18339827

申请日：2023-06-22

申请人： INTEL CORPORATION

发明人： Altug Koker ,  Abhishek R. Appu ,  Kiran C. Veernapu ,  Joydeep Ray ,  Balaji Vembu ,  Prasoonkumar Surti ,  Kamal Sinha ,  Eric J. Hoekstra ,  Wenyin Fu ,  Nikos Kaburlasos ,  Bhushan M. Borole ,  Travis T. Schluessler ,  Ankur N. Shah ,  Jonathan Kennedy

IPC分类号： G09G3/06 ,  G06F1/3203 ,  G06F1/3209 ,  G06F1/3212 ,  G06F1/3218 ,  G06F1/3231 ,  G06F1/324 ,  G06F3/01 ,  G06F11/07 ,  G06F11/30 ,  H04W52/02 ,  H04M1/72448

CPC分类号： G06F1/3209 ,  G06F1/3203 ,  G06F1/3212 ,  G06F1/3218 ,  G06F1/3231 ,  G06F1/324 ,  G06F3/01 ,  G06F11/0781 ,  G06F11/3062 ,  H04W52/0258 ,  H04M1/72448 ,  Y02D10/00 ,  Y02D30/70

摘要： Methods and apparatus relating to techniques for avoiding cache lookup for cold cache. In an example, an apparatus comprises logic, at least partially comprising hardware logic, to collect user information for a user of a data processing device, generate a user profile for the user of the data processing device from the user information, and set a power profile a processor in the data processing device using the user profile. Other embodiments are also disclosed and claimed.

公开(公告)号：US20240345643A1

公开(公告)日：2024-10-17

申请号：US18753266

申请日：2024-06-25

申请人： Wacom Co., Ltd.

发明人： Shahrooz Shahparnia ,  Trond Jarle Pedersen ,  John Logan ,  Vemund Kval Bakken ,  Kishore Sundara-Rajan

IPC分类号： G06F1/3203 ,  G06F3/0354 ,  G06F3/044

CPC分类号： G06F1/3203 ,  G06F3/03545 ,  G06F3/0441 ,  G06F3/0442

摘要： In one embodiment, a stylus includes one or more electrodes and one or more computer-readable non-transitory storage media embodying first logic for transmitting signals wirelessly to a device through a touch-sensor of the device. The stylus has a first power mode in which components of the stylus for receiving signals from or transmitting signals to the device are powered off; a second power mode in which components of the stylus for receiving signals from the device are powered on at least periodically and components of the stylus for transmitting signals to the device are powered off; and a third power mode in which components of the stylus for transmitting signals to the device are powered on at least periodically. The media further embodies second logic for transitioning the stylus from one of the first, second, and third power modes to another one of the first, second, and third power modes.

公开(公告)号：US20240310893A1

公开(公告)日：2024-09-19

申请号：US18676855

申请日：2024-05-29

申请人： SambaNova Systems, Inc.

发明人： Junwei ZHOU ,  Youngmoon CHOI ,  Jinuk SHIN

IPC分类号： G06F1/28 ,  G06F1/30 ,  G06F1/3203 ,  G06F9/445

CPC分类号： G06F1/28 ,  G06F9/44505 ,  G06F1/30 ,  G06F1/3203

摘要： An integrated circuit (IC) comprises an array of power base units (PBUs) organized in rows and columns. The IC further includes an array-level power accumulator that includes a power estimation unit (PEU) and two or more column power accumulators (CPAs) coupled with the PEU and the PBUs via dedicated wiring. Additionally, a power clock management controller (PCMC) is linked to the array-level power accumulator. Notably, some CPAs are connected to the array-level power accumulator through dedicated wiring.

公开(公告)号：US12093103B2

公开(公告)日：2024-09-17

申请号：US18058650

申请日：2022-11-23

申请人： Microchip Technology Incorporated

发明人： Eric Ching ,  Venkatraman Iyer

IPC分类号： G06F1/00 ,  G06F1/3203 ,  G06F9/4401 ,  G06F13/20 ,  G06F1/3209 ,  G06F1/3215

CPC分类号： G06F1/3203 ,  G06F9/4418 ,  G06F13/20 ,  G06F1/3209 ,  G06F1/3215

摘要： One or more examples relate, generally, to an apparatus. Such an apparatus includes a digital interface, a wake detect logic, and a power management connection. The digital interface may define a physical layer transceiver side of a connection between a physical layer transceiver and a physical layer controller, respectively of a 10SPE physical layer. The wake detect logic may communicate a source of detected wake from the physical layer transceiver to the physical layer controller via the digital interface. The power management connection may operatively couple to an enable connection of a switched voltage regulator.

公开(公告)号：US12093102B2

公开(公告)日：2024-09-17

申请号：US17570718

申请日：2022-01-07

申请人： Dell Products L.P.

发明人： Lucas A. Wilson ,  Dharmesh M. Patel

IPC分类号： G06F1/3203 ,  G06F1/3287 ,  H04L9/08 ,  H04L9/32 ,  H04L67/30

CPC分类号： G06F1/3203 ,  H04L9/3273 ,  H04L67/30

摘要： Methods, systems, and devices for providing computer implemented services using managed systems are disclosed. To provide the computer implemented services, the managed systems may need to operate in a predetermined manner conducive to, for example, execution of applications that provide the computer implemented services. Similarly, the managed system may need access to certain hardware resources (e.g., and also software resources such as drivers, firmware, etc.) to provide the desired computer implemented services. To improve the likelihood of the computer implemented services being provided, the managed systems may be managed using a subscription based model. The subscription model may utilize a highly accessible service to obtain information regarding desired capabilities (e.g., a subscription) of a managed system, and use the acquired information to automatically configure and manage the features and capabilities of the managed systems by powering and depowering select components.

公开(公告)号：US12087395B2

公开(公告)日：2024-09-10

申请号：US17558847

申请日：2021-12-22

申请人： TEXAS INSTRUMENTS INCORPORATED

发明人： Steven Craig Bartling ,  Sudhanshu Khanna

IPC分类号： G06F1/00 ,  G06F1/3203 ,  G06F1/3234 ,  G06F1/3287 ,  G06F3/06 ,  G06F9/4401 ,  G06F11/10 ,  G06F11/14 ,  G06F12/02 ,  G06F13/00 ,  G11C7/22 ,  G11C14/00 ,  H03K3/3562

CPC分类号： G11C7/22 ,  G06F1/3203 ,  G06F1/3234 ,  G06F1/3275 ,  G06F1/3287 ,  G06F3/0679 ,  G06F3/0688 ,  G06F9/4401 ,  G06F9/4406 ,  G06F11/1032 ,  G06F11/1438 ,  G06F11/1469 ,  G06F12/0238 ,  G06F13/00 ,  G11C14/00 ,  H03K3/3562 ,  Y02D10/00 ,  Y02D30/50

摘要： Design and operation of a processing device is configurable to optimize wake-up time and peak power cost during restoration of a machine state from non-volatile storage. The processing device includes a plurality of non-volatile logic element arrays configured to store a machine state represented by a plurality of volatile storage elements of the processing device. A stored machine state is read out from the plurality of non-volatile logic element arrays to the plurality of volatile storage elements. During manufacturing, a number of rows and a number of bits per row in non-volatile logic element arrays are based on a target wake up time and a peak power cost. In another approach, writing data to or reading data of the plurality of non-volatile arrays can be done in parallel, sequentially, or in any combination to optimize operation characteristics.

公开(公告)号：US12081361B2

公开(公告)日：2024-09-03

申请号：US17893692

申请日：2022-08-23

申请人： Mellanox Technologies Ltd.

发明人： Amit Kazimirsky ,  Nir Sucher

IPC分类号： H04L12/40 ,  G06F1/3203 ,  G06F1/3206 ,  G06F1/3234 ,  H04L12/10 ,  H04L43/08

CPC分类号： H04L12/40039 ,  G06F1/3203 ,  G06F1/3206 ,  G06F1/3253 ,  H04L12/10 ,  H04L43/08

摘要： Methods, systems, and machine-readable mediums to predict signal conductor traffic and to transition between signal conductor states in accordance with the predictions. In at least one embodiment, a scoring system is used to select a prediction method, which is used to determine when to transition a signal conductor between active and inactive states.

公开(公告)号：US20240264823A1

公开(公告)日：2024-08-08

申请号：US18692785

申请日：2022-05-26

申请人： SUZHOU METABRAIN INTELLIGENT TECHNOLOGY CO., LTD.

发明人： Bo JIANG

IPC分类号： G06F8/65 ,  G06F1/3203

CPC分类号： G06F8/65 ,  G06F1/3203

摘要： Provided are a method for upgrading the CPLD and a CPLD upgrading system, and a computer-readable storage medium. The system includes a baseboard management controller, a master CPLD and a slave CPLD, the master CPLD sends a power control signal to the controller through the slave CPLD, in response to determining that the master CPLD has completed upgrade preparation, the baseboard management controller setting the upgrade-effective signal to an enabled state, to make the slave CPLD lock a current power control signal, and use the current power control signal to control the controller (S101); controlling the master CPLD to perform CPLD upgrade (S102); and when the master CPLD has completed the CPLD upgrade, setting the upgrade-effective signal to a disabled state, to make the slave CPLD release the current power control signal, and use the power control signal sent by the master CPLD to control the controller (S103).

公开(公告)号：US12056535B2

公开(公告)日：2024-08-06

申请号：US17137925

申请日：2020-12-30

申请人： ATI Technologies ULC

发明人： Indrani Paul ,  Leonardo De Paula Rosa Piga ,  Mahesh Subramony ,  Sonu Arora ,  Donald Cherepacha ,  Adam N C Clark

IPC分类号： G06F9/50 ,  G06F1/3203 ,  G06F1/3234 ,  G06F1/324 ,  G06F1/3296 ,  G06F11/30 ,  G06F11/34

CPC分类号： G06F9/505 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3275 ,  G06F1/3296 ,  G06F9/5016 ,  G06F11/3037 ,  G06F11/3062 ,  G06F11/3409 ,  G06F2209/501 ,  G06F2209/508

摘要： Methods and apparatus employ a plurality of heterogeneous compute units and a plurality of non-compute units operatively coupled to the plurality of compute units. Power management logic (PML) determines a memory bandwidth level associated with a respective workload running on each of a plurality of heterogeneous compute units on an integrated circuit (IC), and adjusts a power level of at least one non-compute unit of a memory system on the IC from a first power level to a second power level, based on the determined memory bandwidth levels. Memory access latency is also taken into account in some examples to adjust a power level of non-compute units.