公开(公告)号：US20240310893A1

公开(公告)日：2024-09-19

申请号：US18676855

申请日：2024-05-29

Applicant: SambaNova Systems, Inc.

Inventor： Junwei ZHOU ,  Youngmoon CHOI ,  Jinuk SHIN

IPC: G06F1/28 ,  G06F1/30 ,  G06F1/3203 ,  G06F9/445

CPC classification number: G06F1/28 ,  G06F9/44505 ,  G06F1/30 ,  G06F1/3203

Abstract: An integrated circuit (IC) comprises an array of power base units (PBUs) organized in rows and columns. The IC further includes an array-level power accumulator that includes a power estimation unit (PEU) and two or more column power accumulators (CPAs) coupled with the PEU and the PBUs via dedicated wiring. Additionally, a power clock management controller (PCMC) is linked to the array-level power accumulator. Notably, some CPAs are connected to the array-level power accumulator through dedicated wiring.

公开(公告)号：US20240085966A1

公开(公告)日：2024-03-14

申请号：US18132393

申请日：2023-04-08

Applicant: SambaNova Systems, Inc.

Inventor： Darshan GANDHI ,  Manish K. SHAH ,  Raghu PRABHAKAR ,  Gregory Frederick GROHOSKI ,  Youngmoon CHOI ,  Jinuk SHIN

IPC: G06F1/30 ,  G06F1/08

CPC classification number: G06F1/305 ,  G06F1/08

Abstract: A method includes analyzing a dataflow graph to generate configuration information loadable into an integrated circuit. The dataflow graph specifies operations to be performed and data dependencies between the operations. The configuration information is usable by the integrated circuit to configure compute units of the integrated circuit to perform respective one or more of the operations of the dataflow graph, control data flow between the compute units to accomplish the data dependencies between the respective operations performed by the compute units, and control when each compute unit starts to perform the respective operations on the data to mitigate supply voltage droop caused by a time rate of change of current drawn by the integrated circuit through inductive loads of the integrated circuit.

公开(公告)号：US20240085967A1

公开(公告)日：2024-03-14

申请号：US18132394

申请日：2023-04-08

Applicant: SambaNova Systems, Inc.

Inventor： Darshan GANDHI ,  Manish K. SHAH ,  Raghu PRABHAKAR ,  Gregory Frederick GROHOSKI ,  Youngmoon CHOI ,  Jinuk SHIN

IPC: G06F1/30 ,  G01R31/27 ,  G06F1/28 ,  G06F1/324

CPC classification number: G06F1/305 ,  G01R31/275 ,  G06F1/28 ,  G06F1/324

Abstract: An integrated circuit (IC) includes an array of compute units. Each compute unit is configured such that, when transitioning from not processing data to processing data, the compute unit makes an individual contribution to an aggregate time rate of change of current drawn by the IC. Control circuitry is configurable to, for each compute unit of the array of compute units, control when the compute unit is eligible to transition from not processing data to processing data relative to when the other compute units start processing data to mitigate supply voltage overshoot caused by the aggregate time rate of change of current drawn by the IC through inductive loads of the IC.

公开(公告)号：US20230205293A1

公开(公告)日：2023-06-29

申请号：US18089891

申请日：2022-12-28

Applicant: SambaNova Systems, Inc.

Inventor： Junwei ZHOU ,  Youngmoon CHOI ,  Jinuk SHIN

IPC: G06F1/28 ,  G06F9/445

CPC classification number: G06F1/28 ,  G06F9/44505

Abstract: A processor IC has multiple power base units (PBUs), arranged in an array. Each PBU includes a switch, a memory unit and a compute unit. It further includes a power estimator for the switch, memory unit, and compute unit. The PBUs communicate with an array-level power accumulator via dedicated wiring. Communication via the dedicated wiring may use timestamps to ensure time-accurate aggregate estimates. The switch power estimator estimates dissipation based on port activity. The memory power estimator estimates dissipation based on read and write activity and bit toggling in the memory. The compute power estimator estimates power based on monitoring input data zero values, bit toggling, instruction type, and activity of reconfigurable processing units. The array-level power accumulator calculates the array-level nominal dynamic power estimate. A power clock management controller scales the dynamic power estimate for the actual clock frequency and measured supply voltage, and adds a static power estimate.

公开(公告)号：US20240094794A1

公开(公告)日：2024-03-21

申请号：US18132392

申请日：2023-04-08

Applicant: SambaNova Systems, Inc.

Inventor： Darshan GANDHI ,  Manish K. SHAH ,  Raghu PRABHAKAR ,  Gregory Frederick GROHOSKI ,  Youngmoon CHOI ,  Jinuk SHIN

IPC: G06F1/3206 ,  G06F1/08

CPC classification number: G06F1/3206 ,  G06F1/08

Abstract: An integrated circuit (IC) includes an array of statically reconfigurable compute units for separation into mutually exclusive groups. Each group includes statically reconfigurable number of compute units. Each compute unit includes a register statically reconfigurable with a group identifier that identifies which group the compute unit belongs to, a counter statically reconfigurable to synchronously increment with the counters of all the other compute units such that all the counters have the same value each clock cycle, and control circuitry that prevents the compute unit from starting to process data until the counter value matches the identifier. According to operation of the register, the counter, and the control circuitry, no more than the statically reconfigurable number of the compute units are allowed to start processing data concurrently to mitigate supply voltage droop caused by a time rate of change of current drawn by the IC through inductive loads of the IC.

公开(公告)号：US20240085965A1

公开(公告)日：2024-03-14

申请号：US18132390

申请日：2023-04-08

Applicant: SambaNova Systems, Inc.

Inventor： Darshan GANDHI ,  Manish K. SHAH ,  Raghu PRABHAKAR ,  Gregory Frederick GROHOSKI ,  Youngmoon CHOI ,  Jinuk SHIN

IPC: G06F1/30 ,  G01R31/27 ,  G06F1/28 ,  G06F1/324

CPC classification number: G06F1/305 ,  G01R31/275 ,  G06F1/28 ,  G06F1/324

Abstract: An integrated circuit (IC) includes an array of compute units. Each compute unit is configured such that, when transitioning from not processing data to processing data, the compute unit makes an individual contribution to an aggregate time rate of change of current drawn by the IC. Control circuitry is configurable to, for each compute unit of the array of compute units, control when the compute unit is eligible to transition from not processing data to processing data relative to when the other compute units start processing data to mitigate supply voltage droop caused by the aggregate time rate of change of current drawn by the IC through inductive loads of the IC.