公开(公告)号：US20230205293A1

公开(公告)日：2023-06-29

申请号：US18089891

申请日：2022-12-28

申请人： SambaNova Systems, Inc.

发明人： Junwei ZHOU ,  Youngmoon CHOI ,  Jinuk SHIN

IPC分类号： G06F1/28 ,  G06F9/445

CPC分类号： G06F1/28 ,  G06F9/44505

摘要： A processor IC has multiple power base units (PBUs), arranged in an array. Each PBU includes a switch, a memory unit and a compute unit. It further includes a power estimator for the switch, memory unit, and compute unit. The PBUs communicate with an array-level power accumulator via dedicated wiring. Communication via the dedicated wiring may use timestamps to ensure time-accurate aggregate estimates. The switch power estimator estimates dissipation based on port activity. The memory power estimator estimates dissipation based on read and write activity and bit toggling in the memory. The compute power estimator estimates power based on monitoring input data zero values, bit toggling, instruction type, and activity of reconfigurable processing units. The array-level power accumulator calculates the array-level nominal dynamic power estimate. A power clock management controller scales the dynamic power estimate for the actual clock frequency and measured supply voltage, and adds a static power estimate.

公开(公告)号：US20240310893A1

公开(公告)日：2024-09-19

申请号：US18676855

申请日：2024-05-29

申请人： SambaNova Systems, Inc.

发明人： Junwei ZHOU ,  Youngmoon CHOI ,  Jinuk SHIN

IPC分类号： G06F1/28 ,  G06F1/30 ,  G06F1/3203 ,  G06F9/445

CPC分类号： G06F1/28 ,  G06F9/44505 ,  G06F1/30 ,  G06F1/3203

摘要： An integrated circuit (IC) comprises an array of power base units (PBUs) organized in rows and columns. The IC further includes an array-level power accumulator that includes a power estimation unit (PEU) and two or more column power accumulators (CPAs) coupled with the PEU and the PBUs via dedicated wiring. Additionally, a power clock management controller (PCMC) is linked to the array-level power accumulator. Notably, some CPAs are connected to the array-level power accumulator through dedicated wiring.