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    LOW POWER MULTIBIT FLIP-FLOP FOR STANDARD CELL LIBRARY
    2.
    发明公开
    LOW POWER MULTIBIT FLIP-FLOP FOR STANDARD CELL LIBRARY 审中-公开

    公开(公告)号：US20240339992A1

    公开(公告)日：2024-10-10

    申请号：US18202671

    申请日：2023-05-26

    申请人： SAMSUNG ELECTRONICS CO., LTD.

    发明人： Mitesh GOYAL ,  Hareharan NAGARAJAN ,  Abhishek GHOSH ,  CHIRANSHU BANTHIA

    IPC分类号： H03K3/3562 ,  G01R31/3185 ,  H03K3/012

    CPC分类号： H03K3/35625 ,  G01R31/318544 ,  G01R31/318594 ,  H03K3/012

    摘要： A multibit flip flop is provided. The multibit flip flop includes: a first stage one-bit flip flop; and a second stage one-bit flip flop, wherein the first stage one-bit flip flop and the second stage one-bit flip flop are configured to share a common clock signal. The first stage one-bit flip flop and the second stage one-bit flip flop are configured to use an inter cell scan input transfer function in a sequential manner. The first stage one-bit flip flop is further configured to provide a scan output signal based on a scan input signal provided at an input port of the first stage one-bit flip flop. The second stage one-bit flip flop is further configured to provide a scan final output signal based on the scan output signal that is provided at an input port of the second stage one-bit flip flop.

    Semiconductor device
    5.
    发明授权
    Semiconductor device 有权

    公开(公告)号：US11949413B2

    公开(公告)日：2024-04-02

    申请号：US17698903

    申请日：2022-03-18

    申请人： Nuvoton Technology Corporation Japan

    发明人： Kazuyuki Nakanishi ,  Akio Hirata

    IPC分类号： H01L23/522 ,  H01L27/02 ,  H03K3/3562 ,  H03K19/007

    CPC分类号： H03K19/0075 ,  H01L23/522 ,  H01L27/0203 ,  H03K3/35625

    摘要： A semiconductor device according to an aspect of the present disclosure includes: a plurality of line layers; a first line; and a second line that is not connected to the first line and is redundantly provided to transfer a signal having a level same as a level of a signal transferred through the first line. The first line and the second line are included in different layers out of the plurality of line layers, and a distance between the first line and the second line is longer than an interlayer distance between line layers next to each other out of the plurality of line layers.

    Storage element with clock gating
    8.
    发明授权
    Storage element with clock gating 有权

    公开(公告)号：US11463074B2

    公开(公告)日：2022-10-04

    申请号：US17070086

    申请日：2020-10-14

    申请人： Infineon Technologies AG

    发明人： Thomas Kuenemund ,  Thomas Poeppelmann

    IPC分类号： H04L9/30 ,  H04L9/40 ,  G09C1/00 ,  H03K3/012 ,  H04L9/00 ,  H04L9/14 ,  H03K3/3562 ,  H04L9/06 ,  H04L9/08 ,  H03K3/038

    摘要： A storage element that is operable based on a system clock signal, the storage element including a clock gating circuitry configured to generate a gated clock signal based on at least one Boolean signal and the system clock signal or a preprocessed system clock signal, wherein the clock gating circuitry comprises physical connections of small capacitance such that tapping of at least one of the physical connections results in a hold-time violation. Also, a hardware-based cryptography accelerator or a secured processing system including at least one such storage element, and a method for operating at least one storage element.

    LOW POWER SEQUENTIAL CIRCUIT APPARATUS
    9.
    发明申请
    LOW POWER SEQUENTIAL CIRCUIT APPARATUS 有权

    公开(公告)号：US20220278675A1

    公开(公告)日：2022-09-01

    申请号：US17625706

    申请日：2020-07-08

    申请人： Intel Corporation

    发明人： Tzvika LUSTMAN ,  Avi YONA ,  Yizhar TSUR

    IPC分类号： H03K3/3562 ,  H03K3/012 ,  H03K3/037

    摘要： A latch and/or flip-flop with reduced dynamic capacitance for the clock node. Power associated with the clock node is reduced without timing impact. Merely two clock devices and merely the signal on the clock input pin toggles when the data does not change. As such, power is reduced. Further, the latch is interrupted-based with no contention or jamming issues. The latch can be configured as master and slave latches to form a flip-flop.

    FAULT RESILIENT FLIP-FLOP WITH BALANCED TOPOLOGY AND NEGATIVE FEEDBACK
    10.
    发明申请
    FAULT RESILIENT FLIP-FLOP WITH BALANCED TOPOLOGY AND NEGATIVE FEEDBACK 有权

    公开(公告)号：US20220190813A1

    公开(公告)日：2022-06-16

    申请号：US17118476

    申请日：2020-12-10

    申请人： QUALCOMM Incorporated

    发明人： Hari RAO

    IPC分类号： H03K3/3562 ,  H03K19/096 ,  H03K19/003 ,  H03K17/62 ,  H03K3/037 ,  H03K19/0185

    摘要： The disclosure relates to a latch including a first inverter with a first pair of field effect transistors (FETs) configured with a first channel width to length ratio (W/L), and a second inverter with a second pair of FETs configured with a second W/L different than the first W/L. Another latch includes first and second inverters; a first negative feedback circuit including first and second FETs coupled between first and second voltage rails, the input of the first inverter coupled between the first and second FETs, and the first and second FETs including gates coupled to an output of the first inverter; and a second negative feedback circuit including third and fourth FETs coupled between the first and second voltage rails, the input of the second inverter coupled between the third and fourth FETs, and the third and fourth FETs including gates coupled to an output of the second inverter.