公开(公告)号：US20190170563A1

公开(公告)日：2019-06-06

申请号：US16013199

申请日：2018-06-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangkil Lee ,  Yusin Yang ,  Sung Yoon Ryu ,  Q-Han Park ,  Hyun Lee

IPC: G01F25/00 ,  G01F15/02

Abstract: Disclosed are mass flow controllers, apparatuses for manufacturing semiconductor devices, and methods of maintenance thereof. The mass flow controller may control an amount of a gas provided into a chamber. The mass flow controller may be configured to obtain an absolute volume of the gas provided into the chamber at a standard flow rate when the mass flow controller is initially used. The mass flow controller may be configured to obtain a detected flow rate of the gas provided at a measured flow rate after the mass flow controller has been used for a predetermined time. The mass flow controller may be configured to compare the detected flow rate and the standard flow rate to verify a full-scale error in the measured flow rate.

公开(公告)号：US10230373B2

公开(公告)日：2019-03-12

申请号：US15139949

申请日：2016-04-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ah-Reum Kim ,  Hyun Lee ,  Min-Su Kim

IPC: H03K3/356 ,  H03K19/0185 ,  H03K19/00 ,  H03K3/037 ,  H03K3/012

Abstract: Provided are semiconductor circuits. A semiconductor circuit includes: a first circuit configured to propagate a value of a first node to a second node based on a voltage level of a clock signal; a second circuit configured to propagate a value of the second node to a third node based on the voltage level of the clock signal; and a third circuit configured to determine a value of the third node based on a voltage level of the second node and the voltage level of the clock signal, wherein the first circuit comprises a first transistor gated to a voltage level of the first node, a second transistor connected in series with the first transistor and gated to the voltage level of the third node, and a third transistor connected in parallel with the first and second transistors and gated to a voltage level of the clock signal to provide the value of the first node to the second node.

公开(公告)号：USRE50010E1

公开(公告)日：2024-06-11

申请号：US17672371

申请日：2022-02-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ah-Reum Kim ,  Hyun Lee ,  Min-su Kim

IPC: H03K3/356 ,  H03K3/012 ,  H03K3/037 ,  H03K19/00 ,  H03K19/0185

CPC classification number: H03K19/01855 ,  H03K3/012 ,  H03K3/037 ,  H03K3/356104 ,  H03K3/356191 ,  H03K19/0013

Abstract: Provided are semiconductor circuits. A semiconductor circuit includes a first circuit configured to propagate a value of a first node to a second node based on a voltage level of a clock signal; a second circuit configured to propagate a value of the second node to a third node based on the voltage level of the clock signal; and a third circuit configured to determine a value of the third node based on a voltage level of the second node and the voltage level of the clock signal, wherein the first circuit comprises a first transistor gated to a voltage level of the first node, a second transistor connected in series with the first transistor and gated to the voltage level of the third node, and a third transistor connected in parallel with the first and second transistors and gated to a voltage level of the clock signal to provide the value of the first node to the second node.

公开(公告)号：US11528018B2

公开(公告)日：2022-12-13

申请号：US16930658

申请日：2020-07-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongwoo Kim ,  Minsu Kim ,  Yonggeol Kim ,  Hyun Lee ,  Hyunchul Hwang

IPC: H03K3/3562 ,  H03K3/037 ,  H03K19/00

Abstract: A flip-flop includes an input switching circuit configured to output an intermediate signal based on an input signal and at least one of a phase of a clock signal or a phase of an inverted clock signal, the phase of the inverted clock signal being opposite to the phase of the clock signal, and block application of a driving voltage to at least one circuit element of the input switching circuit in response to receiving a reset signal representing a reset operation of the flip-flop, and a latch circuit configured to generate an output signal based on the intermediate signal according to the at least one of the phase of the clock signal or the phase of the inverted clock signal.

公开(公告)号：US09867283B2

公开(公告)日：2018-01-09

申请号：US15197736

申请日：2016-06-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jin-gyu Kim ,  Hyun Lee ,  Dong-han Kim

IPC: H05K1/03 ,  H05K1/02 ,  H01L23/498 ,  H01L21/48 ,  H05K3/00

CPC classification number: H05K1/0271 ,  H01L21/4846 ,  H01L23/145 ,  H01L23/49838 ,  H05K1/03 ,  H05K1/0366 ,  H05K3/0011 ,  H05K2201/0287 ,  H05K2201/029 ,  H05K2201/0293 ,  H05K2201/2009

Abstract: A package board includes a stack structure that includes a circuit layer and a fiber layer. The fiber layer includes at least one first fiber that extends in a first direction and is a non-woven fiber. Also, a prepreg includes a first fiber that is a non-woven fiber; a plurality of second fibers that are spaced apart from the first fiber and are woven fibers; and an insulating layer that fills gaps between the first fiber and the plurality of second fibers.

公开(公告)号：US12126343B2

公开(公告)日：2024-10-22

申请号：US17983929

申请日：2022-11-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongwoo Kim ,  Minsu Kim ,  Yonggeol Kim ,  Hyun Lee ,  Hyunchul Hwang

IPC: H03K3/037 ,  H03K3/356 ,  H03K3/3562 ,  H03K19/00

CPC classification number: H03K3/0372 ,  H03K3/0375 ,  H03K3/356008 ,  H03K3/3562 ,  H03K19/0002

Abstract: A flip-flop includes an input switching circuit configured to output an intermediate signal based on an input signal and at least one of a phase of a clock signal or a phase of an inverted clock signal, the phase of the inverted clock signal being opposite to the phase of the clock signal, and block application of a driving voltage to at least one circuit element of the input switching circuit in response to receiving a reset signal representing a reset operation of the flip-flop, and a latch circuit configured to generate an output signal based on the intermediate signal according to the at least one of the phase of the clock signal or the phase of the inverted clock signal.

公开(公告)号：US10586809B2

公开(公告)日：2020-03-10

申请号：US16211496

申请日：2018-12-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ju-Hyun Kang ,  Hyun Lee ,  Min-Su Kim ,  Ji-Kyum Kim ,  Jong-Woo Kim

IPC: H01L27/118 ,  G06F17/50

Abstract: An integrated circuit includes a complex logic cell. The complex logic cell includes a first logic circuit providing a first output signal from a first input signal group and a common input signal group, and a second logic circuit providing a second output signal from a second input signal group and the common input signal group. The first and second logic circuits respectively include first and second transistors formed from a gate electrode, the gate electrode extending in a first direction and receiving a first common input signal of the common input signal group.

公开(公告)号：US20220236950A1

公开(公告)日：2022-07-28

申请号：US17509505

申请日：2021-10-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： HYUNCHUL HWANG ,  Hyun Lee

IPC: G06F7/501 ,  H03K19/20

Abstract: An adder integrated circuit includes a first logic gate group that outputs a first internal signal and a second internal signal based on a first input signal and a second input signal, a second logic gate group that outputs a sum signal based on the second internal signal and a third input signal, and a third logic gate group that outputs a carry signal based on the first internal signal, the second internal signal, and the third input signal.

公开(公告)号：US20210044283A1

公开(公告)日：2021-02-11

申请号：US16831452

申请日：2020-03-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JONGKYU RYU ,  Minsu Kim ,  Ahreum Kim ,  Daeseong Lee ,  Hyun Lee

IPC: H03K3/356 ,  H03K19/20 ,  H03K3/012

Abstract: A semi-dynamic flip-flop includes a semiconductor substrate, first through fourth power rails, and at least one clock gate line. The first through fourth power rails are disposed on the semiconductor substrate, extend in a first direction, and are arranged sequentially in a second direction substantially perpendicular to the first direction. The at least one clock gate line is disposed on the semiconductor substrate, and extends in the second direction to pass through at least two regions among a first region between the first power rail and the second power rail, a second region between the second power rail and the third power rail, and a third region between the third power rail and the fourth power rail. The at least one clock gate line receives an input clock signal.

公开(公告)号：US10673420B2

公开(公告)日：2020-06-02

申请号：US15981415

申请日：2018-05-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyun Lee ,  Dae Seong Lee ,  Minsu Kim ,  Ahreum Kim ,  Chunghee Kim

IPC: H03K3/037 ,  H03K19/20 ,  G06F1/10 ,  G01R31/317 ,  G01R31/3177

Abstract: An electronic circuit includes a first flip-flop, a second flip-flop, and a clock generator. The first flip-flop comprises a first master latch and a first slave latch arranged in order along a first direction. The second flip-flop comprises a second master latch and a second slave latch arranged in order along a second direction that is opposite to the first direction. The clock generator is arranged between the first master latch and the second master latch and outputs a clock.