公开(公告)号：US20240272089A1

公开(公告)日：2024-08-15

申请号：US18411816

申请日：2024-01-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minsu Kim ,  Seungryeol Oh ,  Jeongho Ahn

IPC: G01N21/956 ,  G01N21/25 ,  G01N21/55 ,  G01N21/88

CPC classification number: G01N21/956 ,  G01N21/255 ,  G01N2021/555 ,  G01N2021/8835 ,  G01N2201/068 ,  G01N2201/127

Abstract: A defect inspection device includes a stage on which a substrate is provided, an objective lens disposed above the stage to project light onto the substrate, a light source configured to emit light onto a main surface of the substrate via the objective lens, a light quantity measurement sensor disposed above the stage and configured to measure an amount of the light that is reflected from a first region of the main surface of the substrate, a light quantity regulator located between the light source and the objective lens and configured to regulate an amount of the light that is emitted from the light source onto the main surface of the substrate.

公开(公告)号：US12015408B2

公开(公告)日：2024-06-18

申请号：US17712465

申请日：2022-04-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunchul Hwang ,  Minsu Kim

IPC: H03K3/012 ,  H03K3/013 ,  H03K3/356

CPC classification number: H03K3/356191 ,  H03K3/012 ,  H03K3/013 ,  H03K3/356121

Abstract: A flip flop includes a precharge circuit configured to charge a first node by bridging a power voltage node and the first node, the charging of the first node by the precharge circuit according to a voltage level of a clock signal, the charging of the first node by the precharge circuit based on at least two PMOS transistors arranged in series, a discharge circuit configured to discharge the first node by bridging the first node and a ground node, the discharging of the first node according to an input signal and the clock signal, and a second node configured to be charged or discharged, the charging and the discharging of the second node according to a voltage level of the first node.

公开(公告)号：US11082044B2

公开(公告)日：2021-08-03

申请号：US16845135

申请日：2020-04-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chanhee Park ,  Jongwoo Kim ,  Minsu Kim

IPC: H03K3/00 ,  H03K17/16 ,  H03K19/003 ,  G11C5/14 ,  H03K19/00 ,  H03K17/687

Abstract: An integrated circuit is provided. The integrated circuit includes a power gating circuit configured to receive a power supply voltage from a first power line and to output a first driving voltage to a first virtual power line and a logic circuit electrically connected to the first virtual power line and configured to receive power from the power gating circuit. The power gating circuit includes a first p-type transistor and a first n-type transistor connected in parallel between the first power line and the first virtual power line.

公开(公告)号：US11057026B2

公开(公告)日：2021-07-06

申请号：US16831452

申请日：2020-03-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jongkyu Ryu ,  Minsu Kim ,  Ahreum Kim ,  Daeseong Lee ,  Hyun Lee

IPC: H03K3/356 ,  H03K3/012 ,  H03K19/20

Abstract: A semi-dynamic flip-flop includes a semiconductor substrate, first through fourth power rails, and at least one clock gate line. The first through fourth power rails are disposed on the semiconductor substrate, extend in a first direction, and are arranged sequentially in a second direction substantially perpendicular to the first direction. The at least one clock gate line is disposed on the semiconductor substrate, and extends in the second direction to pass through at least two regions among a first region between the first power rail and the second power rail, a second region between the second power rail and the third power rail, and a third region between the third power rail and the fourth power rail. The at least one clock gate line receives an input clock signal.

公开(公告)号：US10990742B2

公开(公告)日：2021-04-27

申请号：US16933281

申请日：2020-07-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong Kyu Ryu ,  Minsu Kim

IPC: G06F30/30 ,  G06F30/392 ,  H01L29/66 ,  H01L27/02 ,  H01L27/118

Abstract: A semiconductor device includes a first standard cell and a second standard cell. A single diffusion break region extending in a first direction is formed in the first standard cell, and a first edge region extending in the first direction and having a maximum cutting depth in a depth direction perpendicular to the first direction is in the first standard cell. A double diffusion break region extending in the first direction is formed in the second standard cell, and a second edge region extending in the first direction and having the maximum cutting depth in the depth direction is formed in the second standard cell.

公开(公告)号：US09354686B2

公开(公告)日：2016-05-31

申请号：US14739360

申请日：2015-06-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minsu Kim ,  Chihyun Cho

IPC: G06F1/32

CPC classification number: G06F1/3206 ,  G06F1/3215 ,  G06F1/3265 ,  G06F1/3287 ,  G06F11/3003 ,  G06F11/3062 ,  G06F2201/865 ,  Y02D10/153 ,  Y02D50/20

Abstract: An electronic device and a method operative therein monitor automatic wakeup events that occur during a power save mode. Wakeup events are monitored for respective applications executable within the electronic device. Applications with processing activity during the power save mode are then listed, on the basis of at least the monitored wakeup events. An indication of which apps are consuming battery power during the power save mode can then be obtained.

Abstract translation: 一种在其中操作的电子设备和方法中，监视在节电模式期间发生的自动唤醒事件。 对在电子设备内可执行的相应应用来监视唤醒事件。 至少在监控的唤醒事件的基础上，列出了节能模式下具有处理活动的应用程序。 然后可以获得在省电模式期间哪些应用正在消耗电池电力的指示。

公开(公告)号：US20250014645A1

公开(公告)日：2025-01-09

申请号：US18443463

申请日：2024-02-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minsu Kim ,  Hongsoo Jeon

IPC: G11C16/08 ,  G11C5/06 ,  G11C16/04 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

Abstract: A nonvolatile memory device includes first and second semiconductor layers and pass transistors. The first semiconductor layer includes wordlines that extend in a first direction and bitlines that extend in a second direction, and further includes a first substrate and a memory cell array. The memory cell array is on the first substrate and connected to the wordlines and the bitlines. The second semiconductor layer is arranged with respect to the first semiconductor layer in a third direction, and includes a second substrate and a peripheral circuit. The peripheral circuit is on the second substrate and controls the memory cell array. The pass transistors are connected to the wordlines and control an electrical connection between the memory cell array and the peripheral circuit. A first part of the pass transistors are in the first semiconductor layer, and a second part of the pass transistors are in the second semiconductor layer.

公开(公告)号：US11988712B2

公开(公告)日：2024-05-21

申请号：US17551974

申请日：2021-12-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chunghee Kim ,  Ahreum Kim ,  Minsu Kim ,  Seungman Lim

IPC: G01R31/3185

CPC classification number: G01R31/318541

Abstract: A multi-bit flip-flop includes a first flip-flop having a first output driver connected to a first output pin and arranged on a first row, a second flip-flop including a second output driver electrically connected to a second output pin and arranged on a second row, and an internal hold buffer connected to the first output driver on the first row and the second flip-flop on the second row.

公开(公告)号：US11784647B2

公开(公告)日：2023-10-10

申请号：US17503791

申请日：2021-10-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyunchul Hwang ,  Minsu Kim ,  Janghwan Yoon

IPC: H03K19/096 ,  H03K19/20

CPC classification number: H03K19/0963 ,  H03K19/20

Abstract: An integrated circuit includes a first circuit, a second circuit, and an inverter. The first circuit receives a first input signal, an inverted clock signal, a first logic level of a first output node, and a logic level of a second output node to determine a second logic level of a first output node. The second circuit receives the first input signal, the clock signal, the first logic level, and the second logic level to determine a logic level of the second output node. The inverter receives a second input signal to output the inverted second input signal to the first circuit or the second circuit. A logic level of the first output node or a logic level of the second output node is output as an output signal when a logic level of the clock signal is a first logic level.

公开(公告)号：US11236455B2

公开(公告)日：2022-02-01

申请号：US16303129

申请日：2016-12-21

Applicant: Samsung Electronics Co., Ltd

Inventor： Atsushi Ohyagi ,  Nobuhiko Shinohara ,  Minsu Kim ,  Hiroki Takita

IPC: D06F33/00 ,  D06F37/30 ,  D06F33/48 ,  D06F39/08 ,  D06F103/18 ,  D06F103/26 ,  D06F34/16

Abstract: A control unit comprises a calculation unit, a determination unit, and a motor rotation control unit. The calculation unit calculates the rate of change in water level, which indicates the amount of change in water level per a predetermined period of time, on the basis of the result of sensing by a water level sensor in connection with a water supply stroke. The determination unit determines whether laundry having a waterproof property is contained in a drum or not on the basis of the rate of change in water level during the water supply stroke calculated by the calculation unit. When it is determined that laundry having a waterproof property is contained in the drum, the motor rotation control unit controls the operation of a driving motor such that the drum is rotated at a predetermined number of rotations or less during the dewatering stroke.