公开(公告)号：US20240243746A1

公开(公告)日：2024-07-18

申请号：US18621934

申请日：2024-03-29

申请人： BITMAIN TECHNOLOGIES INC.

发明人： Hao YAN ,  Lei Wang ,  An Zhao

IPC分类号： H03K19/0185 ,  H03K3/356 ,  H03K19/096

CPC分类号： H03K19/018528 ,  H03K3/35613 ,  H03K19/096

摘要： Provided is a dynamic latch, including: a substrate; a data transmission unit, including a first transmission gate and a second transmission gate, in which an input end of the first transmission gate is connected to an input end of the second transmission gate, and an output end of the first transmission gate is connected to an output end of the second transmission gate; a data output unit, including a first inverter, in which an input end of the first inverter is connected to the output ends of the two transmission gates, a first region of the substrate is adjacent to a second region thereof and oxide diffusion regions in two regions are continuous, drain regions of the two transmission gates are respectively located on opposite sides in the first region, and source regions of the two transmission gates are located between the drain regions of the two transmission gates.

公开(公告)号：US12022014B2

公开(公告)日：2024-06-25

申请号：US18064617

申请日：2022-12-12

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Shih-Lien Linus Lu ,  Jui-Che Tsai ,  Cheng-En Lee

IPC分类号： H04L9/32 ,  H01L21/8238 ,  H03K19/096 ,  H04L9/08

CPC分类号： H04L9/3278 ,  H01L21/823807 ,  H03K19/0963 ,  H04L9/0866 ,  H04L2209/12

摘要： A PUF generator includes a difference generator circuit with first and second transistors having a first predetermined VT. The difference generator circuit is configured to provide a first output signal for generating a PUF signature based on respective turn on times of the first and second transistors. An amplifier includes a plurality of transistors having a second predetermined VT. The amplifier is configured to receive the first output signal and output the PUF signature.

公开(公告)号：US12015515B2

公开(公告)日：2024-06-18

申请号：US17845860

申请日：2022-06-21

申请人： STMicroelectronics S.r.l.

发明人： Valerio Bendotti ,  Nicola De Campo ,  Carlo Curina

IPC分类号： H04L27/36 ,  H03K17/687 ,  H03K19/096 ,  H03K19/21 ,  H04L25/40

CPC分类号： H04L27/36 ,  H03K17/687 ,  H03K19/096 ,  H03K19/21 ,  H04L25/40

摘要： A transmitter circuit receives a PWM input signal and a clock signal. A logic circuit generates a control signal as a function of the clock signal. The control signal is normally set to high, and is periodically set to low for a transmission time interval when an edge is detected in the clock signal. The transmission time interval is shorter than a half clock period of the clock signal. A tri-state transmitter receives the PWM input signal and the control signal, and produces first and a second output signals at first and second transmitter output nodes, respectively. The output signals have a voltage swing between a positive voltage and a reference voltage. An output control circuit is sensitive to the control signal and is coupled to the first and second transmitter output nodes.

公开(公告)号：US20240178835A1

公开(公告)日：2024-05-30

申请号：US18508011

申请日：2023-11-13

申请人： STMICROELECTRONICS S.r.l.

发明人： Carlo CURINA ,  Valerio BENDOTTI

IPC分类号： H03K17/605 ,  H03K3/037 ,  H03K5/133 ,  H03K19/096

CPC分类号： H03K17/605 ,  H03K3/037 ,  H03K5/133 ,  H03K19/096

摘要： In an electronic device, a pulse generator receives an input signal and a clock signal and produces a transmission signal that includes a pulse following each edge of the input signal and of the clock signal. The pulse is low when the input signal is low and high when the input signal is high. A transmitter produces, at its two output nodes, a replica of the transmission signal and the complement of the transmission signal. A galvanic isolation barrier is coupled to the output nodes of the transmitter and produces a differential signal that includes a positive spike at each rising edge of the transmission signal and a negative spike at each falling edge of the transmission signal.

公开(公告)号：US20230018223A1

公开(公告)日：2023-01-19

申请号：US17847241

申请日：2022-06-23

申请人： SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

发明人： Shoki MIYATA ,  Yuto YAKUBO ,  Yoshiyuki KUROKAWA

IPC分类号： H03K19/096 ,  H03M1/46 ,  H03K19/20

摘要： A semiconductor device with reduced power consumption can be provided. The semiconductor device includes a first transistor and a second transistor. The first transistor is a p-channel transistor including silicon in a channel formation region and the second transistor is an n-channel transistor including a metal oxide in a channel formation region. The metal oxide includes indium, an element M (e.g., gallium), and zinc. A gate of the first transistor is electrically connected to a gate of the second transistor, and one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor. The first transistor and the second transistor can each operate in a subthreshold region.

公开(公告)号：US11558055B2

公开(公告)日：2023-01-17

申请号：US17582735

申请日：2022-01-24

申请人： Nuvoton Technology Corporation

发明人： Yung-Chi Lan

IPC分类号： H03K19/096 ,  H03L7/00 ,  G06F1/08 ,  G06F1/12 ,  H03K19/21

摘要： A clock-gating synchronization circuit is provided. The clock-gating synchronization circuit includes a synchronization circuit and clock-gating circuit. The synchronization circuit is configured to perform a synchronization operation to convert a first control signal in a first clock domain into a second control signal in a second clock domain, transmit the second control signal to an electronic circuit, and determine whether the first control signal and the second control signal are the same to generate a first signal. The clock-gating circuit is configured to perform clock gating on the clock signal from a clock generator in the second clock domain according to the first signal to generate a gated clock signal, and transmit the gated clock signal to the electronic circuit and the synchronization circuit, wherein the synchronization operation performed by the synchronization circuit is controlled by the gated clock signal.

公开(公告)号：US20220302917A1

公开(公告)日：2022-09-22

申请号：US17695387

申请日：2022-03-15

申请人： The Board of Trustees of the University of Illinois

发明人： Rakesh Kumar ,  Nathaniel Lewis Bleier

IPC分类号： H03K19/096 ,  G06F9/38 ,  G06F9/30

摘要： An embodiment may involve obtaining a specification of connectivity between a plurality of electronic components, a property library of logical validations, and a set of restrictions for an execution environment of the electronic components, wherein each of the electronic components is associated with at least one of the logical validations; determining that, according to properties in the property library applied to their associated electronic components, a subset of the electronic components exhibit invariance within the execution environment; based on the subset of the electronic components that exhibit invariance within the execution environment, rewiring the connectivity between the plurality of electronic components; and performing logic synthesis on the connectivity between the plurality of electronic components as rewired to simplify at least some of the subset of the electronic components that exhibit invariance within the execution environment.

公开(公告)号：US11431341B2

公开(公告)日：2022-08-30

申请号：US17226648

申请日：2021-04-09

申请人： SK hynix Inc.

发明人： Ji Hyo Kang

IPC分类号： H03K19/096 ,  H03K3/356

摘要： A synchronization circuit includes a precharge circuit and a signal driving circuit. The precharge circuit precharges an output node to a first logic level. The signal driving circuit detects, in synchronization with a second dock signal having a phase leading a first clock signal, a logic level of an input signal and drives, in synchronization with the first clock signal, the output node to a second logic level according to the logic level of the input signal.

公开(公告)号：US20220247411A1

公开(公告)日：2022-08-04

申请号：US17582735

申请日：2022-01-24

申请人： Nuvoton Technology Corporation

发明人： Yung-Chi LAN

IPC分类号： H03K19/096 ,  H03L7/00 ,  G06F1/12 ,  G06F1/08

摘要： A clock-gating synchronization circuit is provided. The clock-gating synchronization circuit includes a synchronization circuit and clock-gating circuit. The synchronization circuit is configured to perform a synchronization operation to convert a first control signal in a first clock domain into a second control signal in a second clock domain, transmit the second control signal to an electronic circuit, and determine whether the first control signal and the second control signal are the same to generate a first signal. The clock-gating circuit is configured to perform clock gating on the clock signal from a clock generator in the second clock domain according to the first signal to generate a gated clock signal, and transmit the gated. clock signal to the electronic circuit and the synchronization circuit, wherein the synchronization operation performed by the synchronization circuit is controlled by the gated clock signal.

公开(公告)号：US20220069823A1

公开(公告)日：2022-03-03

申请号：US17154070

申请日：2021-01-21

申请人： FUJIFILM BUSINESS INNOVATION CORP.

发明人： Hirofumi SASAKI

IPC分类号： H03K19/17758 ,  H03K19/1776 ,  H03K19/096 ,  G06F1/08 ,  G06F1/20

摘要： An information processing apparatus includes a processor connected to a programmable logic circuit. The processor is configured to: allow a first circuit reconfigured in a first region of the programmable logic circuit to execute a process; in parallel with the process of the first circuit, allow a second circuit to be reconfigured in a second region different from the first region; and adjust at least one of a clock frequency used in the process of the first circuit and a clock frequency used in reconfiguration of the second circuit so that a time point at which the process of the first circuit is completed and a time point at which the reconfiguration of the second circuit is completed will become closer to each other.