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14 条记录 (耗时 0.022 秒)

    Electronic circuit testing methods and systems
    4.
    发明授权
    Electronic circuit testing methods and systems 有权

    公开(公告)号：US11979143B2

    公开(公告)日：2024-05-07

    申请号：US17870173

    申请日：2022-07-21

    申请人： STMicroelectronics S.r.l.

    发明人： Nicola Errico ,  Valerio Bendotti ,  Luca Finazzi ,  Gaudenzia Bagnati

    IPC分类号： H03K17/16 ,  H02M3/158

    CPC分类号： H03K17/162 ,  H02M3/158 ,  H03K2217/0063 ,  H03K2217/0072 ,  H03K2217/0081

    摘要： A circuit includes a high-side transistor pair and a low-side transistor pair having a common intermediate node. The high-side transistor pair includes a first transistor having a control node and a current flowpath therethrough configured to provide a current flow line between a supply voltage node and the intermediate node, and a second transistor having a current flowpath therethrough coupled to the control node of the first transistor. The low-side transistor pair includes a third transistor having a control node and a current flowpath therethrough configured to provide a current flow line between the intermediate node and the reference voltage node, and a fourth transistor having a current flowpath therethrough coupled to the control node of the third transistor. Testing circuitry is configured to be coupled to at least one of the second transistor and the fourth transistor to apply thereto a test-mode signal.

    Circuit with hot-plug protection, corresponding electronic device, vehicle and method
    6.
    发明授权
    Circuit with hot-plug protection, corresponding electronic device, vehicle and method 有权

    公开(公告)号：US11888304B2

    公开(公告)日：2024-01-30

    申请号：US16666989

    申请日：2019-10-29

    申请人： STMicroelectronics S.r.l.

    发明人： Vittorio D'Angelo ,  Salvatore Cannavacciuolo ,  Sergio Lecce ,  Valerio Bendotti ,  Orazio Pennisi

    IPC分类号： H02H1/06 ,  H02H9/04 ,  H02J7/00

    CPC分类号： H02H1/063 ,  H02H9/046 ,  H02J7/0014

    摘要： An integrated circuit with a hot-plug protection circuit includes input pins and an output pin. The input pins are electrically coupled to a common node in the hot-plug protection circuit via respective electrical connections. The integrated circuit includes clamping circuitry coupled between the common node and the output pin, the clamping circuitry activatable as a result of a voltage spike applied across the clamping circuitry. The plurality of electrical connections and the clamping circuitry provide respective current discharge paths between the input pins in the input pins and the output pin, the respective current discharge paths configured to become conductive as a result of a voltage spike applied to any of the input pins in the plurality of input pins being transferred to the common node via the respective electrical connection in the plurality of electrical connections electrically coupling said any of said input pins to the common node.

    Self-test circuit, and corresponding device, vehicle and method
    8.
    发明授权
    Self-test circuit, and corresponding device, vehicle and method 有权

    公开(公告)号：US11077755B2

    公开(公告)日：2021-08-03

    申请号：US16420875

    申请日：2019-05-23

    申请人： STMicroelectronics S.r.l.

    发明人： Orazio Pennisi ,  Valerio Bendotti ,  Vanni Poletto

    IPC分类号： B60L3/00 ,  G01R31/385 ,  B60L50/64 ,  H02J7/00 ,  H03M3/00

    摘要： A circuit includes a differential stage configured to provide a differential output signal. An analog-to-digital converter is coupled to first and second output nodes of the differential stage. The analog-to-digital converter is configured to provide an output signal that is a function of the differential output signal from the differential stage. A multiplexer is configured to receive a differential input signal. The multiplexer includes a test switch switchable between a conductive state and a non-conductive state. In the conductive state, the test switch couples the first input node and the second input node of the differential stage. Test signal injection circuitry is activatable to force a differential current through the differential stage. The circuit is selectively switchable between an operational mode and a self-test mode.

    Isolated driver device and method of transmitting information in an isolated driver device
    9.
    发明授权
    Isolated driver device and method of transmitting information in an isolated driver device 有权

    公开(公告)号：US12095603B2

    公开(公告)日：2024-09-17

    申请号：US18146872

    申请日：2022-12-27

    申请人： STMicroelectronics S.r.l.

    发明人： Valerio Bendotti ,  Valerio Gennari Santori

    IPC分类号： H04L27/20 ,  H03K19/20 ,  H04B1/04 ,  H04B1/16 ,  H04L25/49

    CPC分类号： H04L27/20 ,  H03K19/20 ,  H04B1/0466 ,  H04B1/16 ,  H04L25/4902

    摘要： An isolated driver device comprises a first semiconductor die and a second semiconductor die galvanically isolated from each other. The second semiconductor die includes a signal modulator circuit configured to modulate a carrier signal to produce a modulated signal encoding information. A galvanically isolated communication channel implemented in the first semiconductor die and the second semiconductor die is configured to transmit the modulated signal from the second semiconductor die to the first semiconductor die. The second semiconductor die includes: a fault detection circuit configured to detect electrical faults in the second semiconductor die; a logic circuit coupled to the fault detection circuit and configured to assert a modulation bypass signal in response to a fault being detected by the fault detection circuit; and modulation masking circuitry configured to force the modulated signal to a steady value over a plurality of periods of the carrier signal in response to the modulation bypass signal being asserted. The first semiconductor die includes a respective logic circuit sensitive to the modulated signal and configured to detect a condition where the modulated signal has a steady value over a plurality of periods of the carrier signal, and to assert a fault detection signal in response to the condition being detected.