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1.发明公开公开(公告)号：US20240363621A1
公开(公告)日：2024-10-31
申请号：US18770552
申请日：2024-07-11
发明人： Yu-Hung YEH , Wun-Jie LIN , Jam-Wem LEE
IPC分类号： H01L27/02 , H01L23/522 , H01L23/535 , H02H9/04
CPC分类号： H01L27/0288 , H01L23/5223 , H01L23/5228 , H01L23/535 , H01L27/0285 , H01L27/0292 , H02H9/046
摘要： An electrostatic discharge (ESD) protection apparatus and method for fabricating the same are disclosed herein. In some embodiments, the ESD protection apparatus, comprises: a plurality of transistors patterned on a semiconductor substrate during a front-end-of-line (FEOL) process, metal interconnects formed on top of the plurality of transistors during a back-end-of-line (BEOL) process and configured to interconnect the plurality of transistors, and a plurality of passive components formed under the semiconductor substrate in a backside layer during a backside a back-end-of-line (B-BEOL) process, wherein the plurality of passive components are connected to the plurality of transistors through a plurality of vias.
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公开(公告)号：US12132306B2
公开(公告)日：2024-10-29
申请号：US18050773
申请日：2022-10-28
发明人： Wencai Wei , Zhihua Zhang
CPC分类号： H02H7/1257 , H02H9/041 , H05B45/50
摘要： Disclosed is a BRCT clamping absorption circuit with short circuit protection, which relates to the technical field of short-circuit protection, includes a load module, a short-circuit detection module, a short-circuit protection module, a spike absorption module, a rectifying module, a clamping module and a main control module, wherein, the spike absorption module is connected with the load module, the rectifying module is connected with the spike absorption module, and the clamping module is connected with the rectifying module to form a clamping absorption protection for a spike voltage; the main control module is connected with the short-circuit detection module, and is used for controlling the on-off of a load regulator according to the short-circuit signal.
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公开(公告)号：US12132124B2
公开(公告)日：2024-10-29
申请号：US17824149
申请日：2022-05-25
申请人： Marvin Motsenbocker , Xu Ming
发明人： Marvin Motsenbocker , Xu Ming
IPC分类号： H01L29/866 , H01L29/06 , H01L29/16 , H01L29/20 , H01L29/417 , H01L29/66 , H01L29/78 , H02H9/04
CPC分类号： H01L29/866 , H01L29/417 , H01L29/6606 , H01L29/66204 , H02H9/041 , H01L29/0649 , H01L29/1608 , H01L29/2003 , H01L29/7815
摘要： An anti-fuse having two electrical connections is constructed by adding at least one zener diode and resistor to a power MOSFET. When the voltage across the two electrical connections exceeds the zener diode voltage and the maximum gate voltage of the MOSFET, the MOSFET burns out. This shorts out the device which can be used to bypass an LED or other load when that load burns out and forms an open circuit.
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公开(公告)号：US20240355811A1
公开(公告)日：2024-10-24
申请号：US18649658
申请日：2024-04-29
发明人： Huaifeng Wang , Jiangtao Yang , Hang Wang
IPC分类号： H01L27/02 , H02H9/04 , H03K19/003
CPC分类号： H01L27/0274 , H01L27/0255 , H01L27/0277 , H02H9/046 , H03K19/00315
摘要： This application relates to a charging protection circuit. The charging protection circuit implements overcurrent protection by using a four-terminal NMOS switching transistor. In the solution provided in this application, floating management is performed on a Sub port of the four-terminal NMOS switching transistor. Specifically, when the four-terminal NMOS switching transistor is turned on, potential of the Sub port is pulled up, to avoid an excessively large internal resistance of the four-terminal NMOS switching transistor caused by an excessively large voltage between the Sub port and a drain of the four-terminal NMOS switching transistor. In addition, this application further provides a charging circuit and an electronic device.
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公开(公告)号：US12119640B2
公开(公告)日：2024-10-15
申请号：US17831763
申请日：2022-06-03
发明人： Wei Gao , Hongquan Sun , Wangsheng Xie
CPC分类号： H02H9/046 , H01L27/0255 , H01L27/0266
摘要： An electrostatic discharge (ESD) protection circuit is provided to minimize ESD damage to an internal circuit in a CDM model. The ESD protection circuit includes two stages of discharging circuits that are coupled to an IO pin and the internal circuit, a first power clamp circuit, and a second power clamp circuit. The first power clamp circuit is electrically connected to a power rail and a ground rail to discharge a part of a current to the ground, and the second power clamp circuit is electrically connected to a second-stage discharging circuit and the ground rail, so that the other part of the current is discharged to the ground through the second power clamp circuit.
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公开(公告)号：US20240332958A1
公开(公告)日：2024-10-03
申请号：US18193684
申请日：2023-03-31
发明人： Tao Yi Hung , Jam-Wem Lee , Kuo-Ji Chen , Wun-Jie Lin
CPC分类号： H02H9/046 , H02H1/0007
摘要： Systems and methods are provided for a self-biasing electro-static discharge (ESD) power clamp. The ESD power clamp comprises an ESD detection circuit coupled to a positive supply voltage node and a ground voltage node. The ESD detection circuit includes a first node having a first voltage level during a standby mode and a second voltage level during an ESD mode. The ESD power clamp further comprises a discharge circuit coupled to the ESD detection circuit that includes a plurality of discharge elements a self-biasing node having a third voltage level during the standby mode. The third voltage level provides a voltage drop across at least one of the discharge elements that is less than the first voltage level. The discharge circuit provides a high-impedance path during the standby mode and a low-impedance path during the ESD mode.
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公开(公告)号：US20240320186A1
公开(公告)日：2024-09-26
申请号：US18599087
申请日：2024-03-07
申请人： YorChip, Inc.
发明人： Kashmira JOHAL
CPC分类号： G06F15/8023 , G06F13/4282 , G06F15/825 , H01L27/0248 , H02H9/046
摘要： An IC, e.g., a bare die, includes an array of bit-slice tiles. Each bit-slice tile has a ground circuit, a supply circuit, an ESD protection circuit, and a bit-transmit circuit and/or bit-receive circuit for a communication protocol, such as UCIe and/or BoW. Bondpads, using an interconnect layer that can be at or near the top of the metal stack, are placed over one or more bit-slice tiles, and can connect with one or more of the circuits in these one or more of the bit-slice tiles.
To configure the IC, one selects a communication protocol, bump pitch, and number of data bits. Based on the bump pitch, the number of bit-slice tiles per data bits is determined, and tiles are grouped for each bondpad to be used. In each group, the bondpad is created in a top interconnect layer, and connected with a circuit in a bit-slice in the group.-
公开(公告)号：US12100947B2
公开(公告)日：2024-09-24
申请号：US17865809
申请日：2022-07-15
发明人： Chia-Hui Chen , Chia-Jung Chang
CPC分类号： H02H9/046 , H01L27/0266
摘要： Disclosed herein are related to a device for electrostatic discharge (ESD) protection. In one aspect, a device includes an ESD detector to detect an ESD at a pad. In one aspect, the device includes P-type transistors and N-type transistors connected in series with each other. In one aspect, the drive circuit is configured to provide an output signal to the pad. In one aspect, the device includes a first protection circuit operating in a power domain. In one aspect, in response to the ESD detected by the ESD detector, the first protection circuit is configured to disable the P-type transistors. In one aspect, the device includes a second protection circuit operating in another power domain. In one aspect, in response to the ESD detected by the ESD detector, the second protection circuit is configured to disable the N-type transistors.
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公开(公告)号：US12100703B2
公开(公告)日：2024-09-24
申请号：US17897302
申请日：2022-08-29
发明人： Chunping Long , Yong Qiao , Xinyin Wu
CPC分类号： H01L27/0292 , H01L27/027 , H01L27/1251 , H01L27/1259 , H01L27/127 , H01L27/0266 , H01L27/1222 , H01L27/124 , H02H9/045
摘要： Provided an electrostatic protection circuit. The electrostatic protection circuit includes: at least one first transistor and at least one second transistor. A gate electrode and a first electrode of the first transistor are connected to a first signal line, and a second electrode of the first transistor is connected to a second signal line. A gate electrode and a first electrode of the second transistor are connected to the second signal line, and a second electrode of the second transistor is connected to the first signal line. Orthographic projection(s) of a channel and/or a first electrode of the first transistor on a main surface of the array substrate is/are within an orthographic projection of the first signal line on the main surface of the array substrate.
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公开(公告)号：US12088091B2
公开(公告)日：2024-09-10
申请号：US17810682
申请日：2022-07-05
CPC分类号： H02H9/046 , H02H1/0007
摘要： The present disclosure provides an electrostatic discharge (ESD) protection circuit for a chip, including: a monitoring unit, configured to generate a trigger signal when there is an ESD pulse on a power supply pad; a plurality of controllable drive units, connected to the monitoring unit, and each of the controllable drive units being configured to switch an operating state under a control of a control signal, wherein the operating state includes an output state, and the output state refers to generating a drive signal according to the trigger signal; and a discharge transistor, connected to the plurality of controllable drive units, and configured to be turned on under a drive of the drive signal so as to discharge an electrostatic charge to the ground pad.
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