公开(公告)号：US20240355811A1

公开(公告)日：2024-10-24

申请号：US18649658

申请日：2024-04-29

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Huaifeng Wang ,  Jiangtao Yang ,  Hang Wang

IPC: H01L27/02 ,  H02H9/04 ,  H03K19/003

CPC classification number: H01L27/0274 ,  H01L27/0255 ,  H01L27/0277 ,  H02H9/046 ,  H03K19/00315

Abstract: This application relates to a charging protection circuit. The charging protection circuit implements overcurrent protection by using a four-terminal NMOS switching transistor. In the solution provided in this application, floating management is performed on a Sub port of the four-terminal NMOS switching transistor. Specifically, when the four-terminal NMOS switching transistor is turned on, potential of the Sub port is pulled up, to avoid an excessively large internal resistance of the four-terminal NMOS switching transistor caused by an excessively large voltage between the Sub port and a drain of the four-terminal NMOS switching transistor. In addition, this application further provides a charging circuit and an electronic device.

公开(公告)号：US12002801B2

公开(公告)日：2024-06-04

申请号：US17852476

申请日：2022-06-29

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Huaifeng Wang ,  Jiangtao Yang ,  Hang Wang

IPC: H01L27/02 ,  H02H9/04 ,  H03K19/003

CPC classification number: H01L27/0274 ,  H01L27/0255 ,  H01L27/0277 ,  H02H9/046 ,  H03K19/00315

Abstract: This application relates to a charging protection circuit. The charging protection circuit implements overcurrent protection by using a four-terminal NMOS switching transistor. In the solution provided in this application, floating management is performed on a Sub port of the four-terminal NMOS switching transistor. Specifically, when the four-terminal NMOS switching transistor is turned on, potential of the Sub port is pulled up, to avoid an excessively large internal resistance of the four-terminal NMOS switching transistor caused by an excessively large voltage between the Sub port and a drain of the four-terminal NMOS switching transistor. In addition, this application further provides a charging circuit and an electronic device.

公开(公告)号：US20210074853A1

公开(公告)日：2021-03-11

申请号：US17073967

申请日：2020-10-19

Applicant: Huawei Technologies Co., Ltd.

Inventor： Huaifeng Wang

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/40 ,  H01L29/66

Abstract: A semiconductor device, a terminal device, and a manufacturing method, where the device uses a groove-gate structure and a double-longitudinal reduced surface field (RESURF) technology using a longitudinal field plate and a longitudinal PN junction, and a channel is disposed on a bottom of a groove. The device is implemented based on a conventional spit trench gate metal-oxide-semiconductor (MOS) process or a monolithic integrated bipolar-complementary MOS (CMOS)-double-diffused MOS field-effect transistor (DMOS) (BCD) process technology.